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? 2012 freescale semiconductor, inc. all rights reserved. freescale semiconductor data sheet: technical data document number: imx50cec rev. 2, 05/2012 mcimx50 package information plastic package case 416 mapbga 13 x 13 mm, 0.5 mm pitch case 416 popbga 13 x 13 mm, 0.5 mm pitch case 400 mapbga 17 x 17 mm, 0.8 mm pitch ordering information see table 1 on page 7 for ordering information. freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 1 introduction the i.mx50 applications processors (i.mx50) represent freescale semiconducto r?s latest addition to a growing family of multimedia-focused products, offering high performance processing optimized for lowest power consumption. the i.mx50 is optimized for portable multimedia applications and it features freescale?s advanced implementation of the arm cortex-a8? core, which operates at speed as high as 800 mhz. the i.mx50 provides a powerful display architecture, including a 2d graphics processing unit (gpu) and pixel processing pipeline (epxp). in addition, i.mx508 includes a complete integration of the electrophoretic display function. the i.mx50 supports ddr2, lpddr2, and lpddr1 dram at clock rate up to 266 mhz to enable a range of performance and power trade-offs. the flexibility of the i.mx50 architecture allows it to be used in a variety of applications. as the heart of the application chipset, the i.mx50 provides a rich set of interfaces for connecting peripherals, such as wlan, bluetooth?, gps, and displays. i.mx50 applications processors for consumer products 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3. ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 1.4. part number feature comparison . . . . . . . . . . . . . 7 1.5. package feature comparison . . . . . . . . . . . . . . . . 8 2. architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. special signal considerations . . . . . . . . . . . . . . . 17 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . 21 4.2. supply power-up/power-down requirements and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 30 4.4. output buffer impedance characteristics . . . . . . 36 4.5. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6. system modules timing . . . . . . . . . . . . . . . . . . . . 47 4.7. external interface module (eim) . . . . . . . . . . . . . . 59 4.8. dram timing parameters . . . . . . . . . . . . . . . . . . 67 4.9. external peripheral interfaces . . . . . . . . . . . . . . . 72 5. package information and contact assignments . . . . . 100 5.1. 13 x 13 mm, 0.5 mm pitch, 416 pin mapbga package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.2. 13 x 13 mm, 0.5 mm pitch, 416 pin popbga package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3. 17 x 17 mm, 0.8 mm pitch, 400 pin mapbga package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.4. signal assignments . . . . . . . . . . . . . . . . . . . . . . 123 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
i.mx50 applications processors for consumer products, rev. 2 2 freescale semiconductor introduction 1.1 product overview the i.mx50 is designed to enable high-tier portabl e applications by satisfying the performance requirements of advanced operating systems and applications. 1.1.1 dynamic performance scaling freescale?s dynamic voltage and freque ncy scaling (dvfs) allows the devi ce to run at much lower voltage and frequency with ample processing capacity for task s, such as audio decode, resulting in significant power reduction. 1.1.2 multimedia processing powerhouse the multimedia performance of the i.mx50 processor arm cortex-a8 core is boosted by a multi-level cache system, a neon co-processor with simd media processing architecture and 32-bit single-precision floating point support, and two vector floating point co -processors. the system is further enhanced by a programmable smart dma (sdma) controller. 1.1.3 powerful display system the i.mx50 includes support for both standard lcd displa ys as well as electrophoretic displays (e-paper). the display subsystem consists of the following modules: ? electrophoretic display cont roller (epdc) (i.mx508 only) the epdc is a feature-rich, low power, and hi gh-performance direct-drive active matrix epd controller. it is specifically designed to drive e-ink tm epd panels, supporting a wide variety of tft architectures. the goal of the epdc is to provide an efficient soc integration of this functionality for e-paper applications, allowing a si gnificant bill of materials cost savings over an external solution while reaching much higher leve ls of performance and lower power. the epdc module is defined in the context of an optimized hardware/software partitioning and works in conjunction with the epxp (see section 1.1.4, ?graphics accelerators ?). ? enhanced lcd controller interface (elcdif) the elcdif is a high-performance lcd controller interface that supports a rich set of modes and allows interoperability with a wide variety of lcd panels, including dotck/rgb and smart panels. the module also supports synchronous operation with the epxp to allow the processed frames to be passed from the epxp to the elcdif through an on-chip sram buffer. the elcdif can support up to 32-bit interfaces. 1.1.4 graphics accelerators integrated graphics accelerators offload processing from the arm processor, enabling high performance graphic applications at minimum power. ? pixel processing pipeline (epxp) the epxp is a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma mapping, and
introduction i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 3 rotation. the epxp is enhanced with features specifically for grayscale applications working in conjunction with the electrophoretic display controller to form a full grayscale display solution. in addition, the epxp supports traditional pixel/fra me processing paths for still-image and video processing applications, allowing it to interface with the integrated lcd controller (elcdif). ? graphics acceleration the i.mx50 provides a 2d graphics accelerator with performance up to 200 mpix/s. 1.1.5 multilevel memory system the multilevel memory system of the i.mx50 is based on the l1 instruction and data caches, l2 cache, and internal and external memory. the i.mx50 suppor ts many types of external memory devices, including ddr2, lpddr2, lpddr1, nor flash, psram, cellular ram, nand flash (mlc and slc) and onenand?, and managed nand including emmc up to rev. 4.4. 1.1.6 smart speed? technology the i.mx50 device has power management throughout th e soc that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. smart speed technology enables the designer to deliver a feat ure-rich product that requires levels of power that are far less than industry expectations. 1.1.7 interface flexibility the i.mx50 supports connection to a variety of interfaces, including an lcd controller for displays, two high-speed usb on-the-go-capable phys, multiple expansion card ports (high-speed mmc/sdio host and others), 10/100 ethernet controller, and a variet y of other popular interfaces (for example, uart, i 2 c, and i 2 s serial audio). 1.1.8 advanced security the i.mx50 delivers hardware-enabled security features, such as high-assurance boot 4 (hab4) for signed/authenticated firmware images, basic drm support with random private keys and aes encryption/decryption, and storage and programmability of on-chip fuses. 1.2 features the i.mx50 application processor (ap) is based on arm cortex-a8 platform and has the following features: ? mmu, l1 instruction cache, and l1 data cache ? unified l2 cache ? 800 mhz target frequency of the core (including neon, vfpv3, and l1 cache) ? neon coprocessor (simd media processing architecture) and vector floating point (vfp-lite) coprocessor supporting vfpv3
i.mx50 applications processors for consumer products, rev. 2 4 freescale semiconductor introduction the memory system consists of the following components: ? level 1 cache: ? instruction (32 kbyte) ? data (32 kbyte) ? level 2 cache: ? unified instruction and data (256 kbyte) ? level 2 (internal) memory: ? boot rom, including hab (96 kbyte) ? internal multimedia/shared, fast access ram (128 kbyte) ? external memory interfaces: ? 16/32-bit ddr2-533, lpddr2-533, or lpddr1-400 up to a total of 2 gbyte ? 8-bit nand slc/mlc flash with up to 100 mhz synchronous clock rate and up to 32-bit hardware ecc for 1 kbyte block size ? 16/32-bit nor flash with a dedicated 16-bit m uxed-mode interface. i/o muxing logic selects eimv2 port as primary muxing at system boot. ? 16-bit psram, cellular ram ? managed nand, including emmc up to rev 4.4 the i.mx50 introduces a next generation system bus fabric architecture that aggregates various sub-system buses and masters for access to system peripherals and memories. the various bus-systems and components are as follows: ? 64-bit axi fabric (266 mhz)?this bus-fabric is the soc?s central bus aggregation point. ? provides access to all slave targets in the soc: ? rom (romcp) ? on-chip ram (ocram) ? external dram (dram mc) ? external static ram (eim) ? interrupt controller (tzic) ? decode into the ahb max crossbar second level ahb fabric. ? provides arbitration to the following masters in the system: ? arm cpu complex ? pixel processing pipeline (epxp) ? electrophoretic disp lay controller (epdc) ? elcdif lcd display controller ? dcp crypto engine ? bch ecc engine ? max ahb crossbar ?gpu 2d ?sdma
introduction i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 5 ? usboh1 (usb otg and host controller complex) ? fec ethernet controller ? max ahb crossbar (133 mhz)?this connects the various ahb bus sub-segments in the system and provides decode into the following slaves: ? ip-bus 1 (66 mhz)?this bus segment contains peripherals accessible by the arm core and without dma capability ? ip-bus 2 (66 mhz)?this bus segment contains peripherals accessible by the arm core and without dma capability ? apbh dma bridge (133 mhz)?the apbh dma bridge is a master to the max for its memory-side dma operations. the apbh bus is an amba apb slave bus providing peripheral access to many of the high-speed ip blocks on the i.mx50. ? ip-bus 3 (66 mhz)?this third peripheral bus se gment contains peripherals accessible by the arm core and sdma and as such houses peripherals with dma capability. the ip-bus 3 can be accessed by the arm cpu through ip-bus 1 and spba. ? quality of service controller (qosc)?this provid es both soft and dynamic arbitration/priority control. the qosc works in conjunction with the critical display modules such as the elcdif and epdc to provide dynamic priority control, based on real-time metrics. the i.mx50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. the use of hardware accelerators provides both high performance and low power consumption, while freeing up the cpu core for other tasks. the i.mx50 incorporates the following hardware accelerators: ? gpu2dv1?2d graphics accelerator, openvg 1.1, 200 mpix/s performance ? epxp?enhanced pixel processing pipeline off loading key pixel processing operations required to support both lcd and epd display applications the i.mx50 includes the following interfaces to external devices: note not all the interfaces are available simultaneously depending on i/o multiplexer configuration. ?displays: ? epdc (i.mx508 only)?supporting direct-driver tft backplanes beyond 2048 1536 at 106 hz refresh (or 4096 4096 at 20 hz) ? elcdif?supporting beyond sxga + (1400 1050) at 60 hz resolutions with up to a 32-bit display interface ? on the i.mx508, both displays can be active simultaneously. if both displays are active, the elcdif only provides a 16-bit interface due to pin muxing. ? expansion cards: ? four sd/mmc card ?usb: ? one high speed (hs) usb 2.0 otg-capable port with integrated hs usb phy
i.mx50 applications processors for consumer products, rev. 2 6 freescale semiconductor introduction ? one high speed (hs) usb 2.0 host port with integrated hs usb phy ? miscellaneous interfaces: ? one-wire (owire) port ? two i2s/ssi/ac97 ports, supporting up to 1.4 mbps each connected to the audio multiplexer (audmux) providing four external ports ? five uart rs232 ports, up to 4.0 mbps each ? two ecspi (enhanced cspi) ports, up to 66 mbps each plus cspi port, up to 16.6 mbps ? three i 2 c ports, supporting 400 kbps ? fast ethernet controller ieee 802.3, 10/100 mbps ? key pad port (kpp) ? two pulse width modulators (pwm) ? gpio with interrupt capabilities ? secure jtag controller (sjc) the system supports efficient and smart power control and clocking: ? supporting dvfs techniques for low power modes, including auto slow architecture ? power gating-srpg (state retention power gating) for arm core and neon ? support for various levels of system power modes ? flexible clock gating control scheme ? on-chip temperature monitor ? on-chip 32 khz and 24 mhz oscillators ? a total of four plls with the fourth pll provi ding up to eight independently controllable outputs, improving the ease of clocking control, esp ecially for display and connectivity modules security functions are enabled and accelerated by the following hardware: ? secure jtag controller (sjc)?protecting jtag from debug port attacks by regulating or blocking the access to the system debug features ? secure real-time clock (srtc)?tamper resistant rtc with dedicated power domain and mechanism to detect voltage and clock glitches ? advanced high assurance boot (a-hab)?hab with the next embedded enhancements: sha-256, 2048-bit rsa key, version control mechanism, warm boot, csu, and tz initialization
introduction i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 7 1.3 ordering information table 1 provides the ordering information. 1.4 part number feature comparison table 2 provides an overview of the feature differences between the i.mx50 part numbers. table 1. ordering information part number mask set features temperature range ( c) package 1 1 case mapbga is rohs compliant, lead-free msl (moisture sensitivity level) 3. t ambient t junction mcimx508cvk8b n78a full specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch bga case: 416 mapbga mcimx508czk8b n78a full specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch bga case: 416 popbga mcimx508cvm8b n78a full specification 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch bga case: 400 mapbga mcimx507cvm8b n78a no gpu 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch bga case: 400 mapbga mcimx503cvk8b n78a no epd controller 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch bga case: 416 mapbga MCIMX503CVM8B n78a no epd controller 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch bga case: 400 mapbga mcimx503evm8b n78a no epd controller, extended temperature -20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch bga case: 400 mapbga mcimx502cvk8b n78a no gpu, no epd controller 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch bga case: 416 mapbga mcimx502cvm8b n78a no gpu, no epd controller 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch bga case: 400 mapbga mcimx502evm8b n78a no gpu, no epd controller, extended temperature -20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch bga case: 400 mapbga table 2. part number feature comparison part number disabled features comments mcimx508 none mcimx507 gpu
i.mx50 applications processors for consumer products, rev. 2 8 freescale semiconductor introduction 1.5 package feature comparison table 3 provides an overview of the feature and pin differences between the i.mx50 packages. mcimx503 epdc the i.mx503 has the same ball map and iomux as the i.mx508. the epdc pins still exist on the i.mx503, but because the epdc block is disabled, those pins cannot be used for epdc functionality (alt0) and must be configured in the iomux with another alt-mode setting. mcimx502 gpu, epdc the i.mx502 has the same ball map and iomux as the i.mx508. the epdc pins still exist on the i.mx502, but because the epdc block is disabled, those pins cannot be used for epdc functionality (alt0) and must be configured in the iomux with another alt-mode setting. table 3. package feature comparison package dimensions i/o pin differences versus 416 mapbga notes on package differences 416 mapbga 13 x 13 mm, 0.5 mm pitch ? ? usb_otg_vdda25 and usb_h1_vdda25 are shorted together on the 416 mapbga package substrate. ? usb_otg_vdda33 and usb_h1_vdda33 are shorted together on the 416 mapbga package substrate. table 2. part number feature comparison (continued) part number disabled features comments
introduction i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 9 416 popbga 13 x 13 mm, 0.5 mm pitch deleted pins: dram_a10 dram_a11 dram_a12 dram_a13 dram_a14 dram_cas dram_open dram_openfb dram_ras dram_sdba0 dram_sdba1 dram_sdba2 dram_sdclk_1 dram_sdclk_1_b dram_sdodt0 dram_sdodt1 dram_sdwe dram_open dram_openfb added pins: pop_emmc_rst pop_lpddr2_zq0 pop_lpddr2_zq1 pop_lpddr2_1.8v pop_nand_vcc ? the i.mx50 popbga package supports 168-fbga lpddr2 dram memory only. it is not possible to support lpddr1 or ddr2 on the i.mx50 popbga. ? i.mx50 popbga was designed to accommodate a combined lpddr2 / emmc pop memory. the pop emmc device uses the sd3_data[7:0], sd3_clk, and sd3_cmd pins. because the pop emmc i/o and memory supplies are tied together on the substrate, 1.8 v emmc i/o operation is not supported for the pop emmc device. pop_nand_vcc and nvcc_nandf must use a 3 v supply. ? the nvcc_emi_dram power pins supply 1.2 v power to the i.mx50 dram controller as well as the pop lpddr2 dram. ? additional pop package pin descriptions may be found in the special signals considerations section ( table 5 ). ? on the popbga package, the dram address, data, and clock pins are routed to the bottom balls for freescale test purposes only. it is recommended that these bottom dram pins are left unconnected on the customer pcb. ? usb_otg_vdda25 and usb_h1_vdda25 are shorted together on the 416 popbga package substrate. ? usb_otg_vdda33 and usb_h1_vdda33 are shorted together on the 416 popbga package substrate. 400 mapbga 17 x 17 mm, 0.8 mm pitch deleted pins: dram_sdclk_1 dram_sdclk_1_b dram_a14 dram_sdodt1 uart2_cts uart2_rts ? usb_otg_vdda25 and usb_h1_vdda25 are independent and not shorted together on the 400 mapbga package substrate. ? usb_otg_vdda33 and usb_h1_vdda33 are independent and not shorted together on the 400 mapbga package substrate. table 3. package feature comparison (continued) package dimensions i/o pin differences versus 416 mapbga notes on package differences
i.mx50 applications processors for consumer products, rev. 2 10 freescale semiconductor architectural overview 2 architectural overview the following sections provide an architectur al overview of the i.mx50 processor system. 2.1 block diagram figure 1 shows the functional modules in the i.mx50 processor system. figure 1. i.mx50 system block diagram
modules list i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 11 note the numbers in brackets indicate the number of module instances. for example, pwm (2) indicates tw o separate pwm peripherals. 3 modules list the i.mx50 processor contains a variety of dig ital and analog modules that are described in table 4 in alphabetical order. table 4. i.mx50 digital and analog modules block mnemonic block name subsystem brief description arm cortex-a8 arm cortex-a8 platform arm the arm cortex-a8 core platform consists of the arm cortex-a8 processor and its essential sub-blocks. it contains the 32 kbyte l1 instruction cache, 32 kbyte l1 data cache, level 2 cache controller and a 256 kbyte l2 cache. the platform also contains an event monitor and debug modules. it also has a neon co-processor with simd media processing architecture, register file with 32 64-bit general-purpose registers, an integer execute pipeline (alu, shift, mac), dual, single-precision floating point execute pipeline (fadd, fmul), load/store and permute pipeline, and a non-pipelined vector floating point (vfp lite) co-processor supporting vfpv3. epdc electrophoretic display controller display peripherals the epdc is a feature-rich, low power, and high-performance direct-drive active matrix epd controller. it is specifically designed to drive e-ink tm epd panels supporting a wide variety of tft backplanes. epxp enhanced pixel processing pipeline display peripherals a high-performance pixel processor capable of 1 pixel/clock performance for combined operations such as color-space conversion, alpha blending, gamma-mapping, and rotation. the epxp is enhanced with features specifically for grayscale applications. in addition, the epxp supports traditional pixel/frame processing paths for still-im age and video processing applications allowing it to interface with the integrated lcd controller (elcdif). elcdif enhanced lcd interface display peripherals the elcdif is a high-performance lcd controller interface supporting a rich set of modes allowing inter operability with a wide variety of lcd panels, including dotck/rgb and smart panels. the module also supports a synchronous operation with the epxp to allow the processed frames to be passed from the epxp to the elcdif through an on-chip sram buffer. the elcdif can support up to 32-bit interfaces. audmux digital audio mux slave connectivity peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, ssi1 and ssi2) and peripheral serial interfaces (audio and voice codecs). the audmux has six ports (two internal and four external) with identical functionality and programming models. a desired connectivity is achieved by configuring two or more audmux ports. camp-1 clock amplifier clocks, resets, and power control clock amplifier
i.mx50 applications processors for consumer products, rev. 2 12 freescale semiconductor modules list ccm gpc src clock control module global power controller system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, and also for system power management. the system includes four plls. cspi ecspi-1 ecspi-2 configurable spi, enhanced cspi slave connectivity peripherals full-duplex enhanced synchronous serial interface, with data rate up to 66.5 mbit/s (for ecspi, master mode). it is configurable to support master/slave modes, four chip selects to support multiple peripherals. dap tpiu cti debug system system control peripherals the debug system provides real-time trace debug capability of both instructions and data. it supports a trace protocol that is an integral part of the arm real time debug solution (realview). real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, three cross-system triggers (cti), counters, and sequencers. debug access port (dap)?the dap provides real-time access for the debugger without halting the core to system memory and peripheral registers. all debug configuration registers and debugger access to jtag scan chains. dram mc dram memory controller external memory interface the dram mc consists of a dram memory controller and phy, supporting lpddr2, ddr2, and lpddr1 memories with clock frequencies up to 266 mhz with 32-bit interface. it is tightly linked with the system bus fabric and employs advanced arbitration mechanism to maximize dram bandwidth efficiency. eim static memory controller external memory interface the eim is an external static memory and generic host interface. it supports up to a 32-bit interface (through pin-muxing) or a dedicated 16-bit muxed interface. it can be used to interface to psrams (sync and async), nor-flash or any external memory mapped peripheral. bch32/gpmi2 raw nand system with ecc rawnand and ssp peripherals the i.mx50 contains a fully hardware accelerated raw nand flash solution supporting slc and mlc devices. the system consists of the gpmi2 module, which is driven by the apbh dma engine to perform the nand flash interface function (supporting up to onfi2.1). coupled with the gpmi2 is the bch32 hardware error-correction engine which is an axi bus-master and supports up to 32-bits of correction over block sizes up to 1 kbyte (that is, supports up to 2 kbyte code-size). system fabric and qos system fabric and qos system peripherals in order to aggregate the multitude of masters and memory mapped devices, the i.mx50 contains a next-generation amba3 axi bus fabric. in addition, the i.mx50 contains a quality of service controller ip (qosc) which allows both soft priority control and dynamic priority elevation. software priority control works for all masters but dynamic hardware control only works for epdc and elcdif. epit enhanced periodic interrupt timer timer peripherals each epit is a 32-bit set and forget timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. table 4. i.mx50 digital and analog modules (continued) block mnemonic block name subsystem brief description
modules list i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 13 esdhcv3-3 (emmc 4.4) ultra-high- speed multi-media card/ secure digital card host controller, ver. 3 master connectivity peripherals ultra high-speed esdhc, enhanced to support emmc 4.4 standard specification, for 832 mbps. ip is backward compatible to esdhcv2 ip. see complete features listing in esdhcv2 entry below. port 3 is specifically enhanced to support emmc 4.4 specification, for double data rate (832 mbps, 8-bit port). esdhcv2-1 esdhcv2-2 esdhcv2-4 enhanced multi-media card/ secure digital host controller, ver. 2 in enhanced multi-media card/secure digital host controller the ports 1, 2, and 4 are compatible with the mmc system specification version 4.3, full support the generic features of the esdhcv2 module, when serving as sd/mmc host, include the following: ? can be configured either as sd/mmc controller ? supports esd and emmc standard, for sd/mmc embedded type cards ? conforms to sd host controller standard specification version 2.0, full support ? compatible with the sd memory card specification version 1.1 ? compatible with the sdio card specification version 1.2 ? designed to work with sd memory, minisd memory, sdio, minisdio, sd combo, mmc and mmc rs cards ? configurable to work in one of the following modes: ?sd/sdio 1-bit, 4-bit ?mmc 1-bit, 4-bit, 8-bit ? full/high speed mode ? host clock frequency variable between 32 khz to 52 mhz ? up to 200 mbps data transfer for sd/sdio cards using four parallel data lines ? up to 416 mbps data transfer for mmc cards using eight parallel data lines fec fast ethernet controller master connectivity peripherals the ethernet media access controller (mac) is designed to support both 10 mbps and 100 mbps ethernet/ieee std 802.3? networks. an external transceiver interface and transceiver function are required to complete the interface to the media. gpio-1 gpio-2 gpio-3 gpio-4 gpio-5 gpio-6 general purpose i/o modules slave connectivity peripherals these modules are used for general purpose input/output to external ics. each gpio module supports up to 32 bits of i/o. gpt general purpose timer timer peripherals each gpt is a 32-bit free-running or set and forget mode timer with a programmable prescaler and compare and capture register. a timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or tra iling edges of an input pulse. when the timer is configured to operate in ?set and forget? mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. table 4. i.mx50 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx50 applications processors for consumer products, rev. 2 14 freescale semiconductor modules list gpu2dv1 graphics processing unit-2d, ver. 1 display peripherals the gpu2dv1 provides hardware acceleration for 2d graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to hd1080 resolution. i 2 c-1 i 2 c-2 i 2 c-3 i 2 c interface connectivity peripherals i 2 c provides serial interface for controlling peripheral devices. data rates of up to 400 kbps are supported. ocotp controller on-chip otp controller security peripherals the on-chip one-time -programmable (ocotp) rom serves the functions of hardware and software capability bits, freescale operations and unique-id, the customer-programmable cryptography key, and storage of various rom and general purpose configuration bits. iomuxc iomux control slave connectivity peripherals this module enables flexible i/o multiplexing. each i/o pad has default as well as several alternate functions. the alternate functions are software configurable. kpp keypad port slave connectivity peripherals the kpp supports an 8 8 external keypad matrix. the kpp features are as follows: ? open drain design ? glitch suppression circuit design ? multiple keys detection ? standby key press detection owire one-wire interface slave connectivity peripherals one-wire support provided for interfacing with an on-board eeprom, and smart battery interfaces, for example, dallas ds2502. pwm-1 pwm-2 pulse width modulation slave connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images. it can also generate tones. the pwm uses 16-bit resolution and a 4 x 16 data fifo to generate sound. ram 128 kbytes internal ram internal memory the on-chip memory controller (ocram) module, is an interface between the system?s axi bus, to the internal (on-chip) sram memory module. it is used for controlling the 128 kbyte multimedia ram, through a 64-bit axi bus. rom 96 kbytes boot rom internal memory supports secure and regular boot modes. the rom controller supports rom patching. table 4. i.mx50 digital and analog modules (continued) block mnemonic block name subsystem brief description
modules list i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 15 sdma smart direct memory access master connectivity peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system performance by offloading various cores in dynamic data routing. the sdma features list is as follows: ? powered by a 16-bit instruction-set micro-risc engine ? multi-channel dma supports up to 32 time-division multiplexed dma channels ? 48 events with total flexibility to trigger any combination of channels ? memory accesses including linear, fifo, and 2d addressing ? shared peripherals between arm cortex-a8 and sdma ? very fast context-switching with two-level priority-based preemptive multi-tasking ? dma units with auto-flush and prefetch capability ? flexible address management for dma transfers (increment, decrement, and no address changes on source and destination address) ? dma ports can handle uni-directional and bi-directional flows (copy mode) ? up to 8-word buffer for configurable burst transfers for emi ? support of byte-swapping and crc calculations ? a library of scripts and api is available sjc secure jtag controller system control peripherals the secure jtag controller provides a mechanism for regulating jtag access, preventing unauthorized jtag usage while allowing jtag access for manufacturing tests and software debugging. the i.mx50 jtag port provides debug access to several hardware blocks including the arm processor and the system bus, therefore, it must be accessible for initial laboratory bring-up, manufacturing tests and troubleshooting, and for software debugging by authorized entities. however, if the jtag port is left unsecured it provides a method for executing unauthorized program code, getting control over secure applications, and running code in privileged modes. the secure jtag controller provides three different security modes that can be selected through an e-fuse configuration to prevent unauthorized jtag access. spba shared peripheral bus arbiter system control peripherals spba (shared peripheral bus arbiter) is a two-to-one ip bus interface (ip bus) arbiter. srtc secure real time clock security peripherals the srtc incorporates a special system state retention register (ssrr) that stores system parameters during system shutdown modes. this register and all srtc counters are powered by dedicated supply rail nvcc_srtc. the nvcc_srtc can be energized separately even if all other supply rails are shut down. this register is helpful for storing warm boot parameters. the ssrr also stores the system security state. in case of a security violation, the ssrr marks the event (security violation indication). table 4. i.mx50 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx50 applications processors for consumer products, rev. 2 16 freescale semiconductor modules list ssi-1 ssi-2 i2s/ssi/ac97 interface slave connectivity peripherals the ssi is a full-duplex synchronous interface used on the i.mx50 processor to provide connectivity with off-chip audio peripherals. the ssi interfaces connect internally to the audmux for mapping to external ports. the ssi supports a wide variety of protocols (ssi normal, ssi network, i2s, and ac-97), bit depths (up to 24 bits per word), and clock/frame sync options. each ssi has two pairs of 8 x 24 fifos and hardware support for an external dma controller in order to minimize its impact on system performance. the second pair of fifos provides hardware interleaving of a second audio stream, which reduces cpu overhead in use cases where two time slots are being used simultaneously. temperature monitor temp sensor analog the temperature sensor is an internal module to the i.mx50 that monitors the die temperature. uart-1 uart-2 uart-3 uart-4 uart-5 uart interface, ver. 2 slave connectivity peripherals each of the uartv2 modules supports the following serial data transmit/receive protocols and configurations: ? 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) ? programmable bit-rates up to 4 mbps. this is a higher max baud rate relative to the 1.875 mbps, which is specified by the tia/eia-232-f standard. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud ? irda 1.0 support (up to sir speed of 115200 bps) usb-oh-1 usb 2.0 high-speed otg-capable and host ports master connectivity peripherals usb-oh-1 supports usb2.0 hs/fs/ls, and contains: ? one high-speed otg-capable module with integrated hs usb phy ? one high-speed host module with integrated hs usb phy wdog-1 watch dog timer peripherals the watchdog (wdog) timer module protects against system failures by providing a method of escaping from unexpected events or programming errors. the wdog timer supports two comparison points during each counting period. each of the comparison points is configurable to invoke an interrupt to the arm core, and a second point invokes an external event on the wdog line. xtalosc crystal oscillator i/f clocking the xtalosc module combined with an external 24 mhz crystal with load capacitors implements a crystal oscillator. table 4. i.mx50 digital and analog modules (continued) block mnemonic block name subsystem brief description
modules list i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 17 3.1 special signal considerations table 5 lists special signal considerations for the i. mx50. the signal names ar e listed in alphabetical order. the package contact assignments are found in section 5, ?package information and contact assignments.? the signal descriptions are defined in the mcimx50 applications processor reference manual (mcimx50rm). table 5. special signal considerations signal name remarks boot_mode0, boot_mode1 these two input pins are sampled out of reset and set the boot mode. for internal boot, they should be set to 00. for internal fuse only boot, they should be set to 10. for usb downloader, they should be set to 11. the bootmode pins are in the nvcc_reset domain and include an internal 100k pull-up resistor at start-up. boot_config1[7:0], boot_config2[7:0], boot_config3[7:0] these 24 pins are the gpio boot override pins and may be driven at power up to select the boot mode. they are sampled 4 x ckil clock cycles after por is de-asserted. consult the ?system boot? chapter of the reference manual for more details. note that these are not dedicated pins: the boot_config pins appear over 24 pins of the eim interface. bt_lpb_freq[1:0] if the low_batt_gpio (uart4_txd) is asserted at power up, the bt_lpb_freq[1:0] pins will be sampled to determine the arm core frequency. consult the ?system boot? chapter of the reference manual for more details. note that these are not dedicated pins: bt_lpb_freq0 appears on ssi_txfs and bt_lpb_freq1 appears on ssi_txc. chgr_det_b this is the usb charger detect pin. it is an open drain output pin that expects a 100 k pull-up. this pin is asserted low when a usb charger is detected on the otg phy dp and dm. this detection occurs with the application of vbus. this pin is a raw sensor output and care must be taken to follow the system timings outlined in the usb charger specification rev 1.1. the maximum current leakage at this pin is 8.5 a. this pin can be controlled by software control as well. if not used, this pin should be tied to ground or left floating. ckih this is an input to the camps (clock amplifiers), which include on-chip ac-coupling precluding the need for external coupling capacitors. the camps are enabled by default, but the main clocks feeding the on-chip clock tree are sourced from xtal/extal by default. optionally, the use of a low jitter external oscillators to feed ckih (while not required) can be an advantage if low jitter or special frequency clock sources are required by modules sourced by ckih. see ccm chapter in the mcimx50 applications processor reference manual (mcimx50rm) for details on the respective clock trees. after initialization, the camps may be disabled if not used by programming the ccr campx_en field. if disabled, the on-chip camp output is low and the input is irrelevant. ckih is on the nvcc_jtag power domain, so the input clock amplitude should not exceed nvcc_jtag. if unused, the user should tie ckih to gnd for best practice. ckil/eckil the user must tie a fundamental mode 32.768 k crystal across eckil and ckil. the target esr should be 50 k or less. the bias resistor for the amplifier is integrated and approximately 14 m . the target load capacitance for the crystal is approximately 10 pf. the load capacitors on the board should be slightly less than double this value after taking parasitics into account. while driving in an external 32 khz signal into eckil, ckil should be left floating so that it biases. a differential amplifier senses these two pins to propagate the clock inside the i.mx508. care must be taken to minimize external leakages on eckil and ckil. if they are significant to the 14 m feedback or 1 a, then loss of oscillation margin or cessation of oscillation may result.
i.mx50 applications processors for consumer products, rev. 2 18 freescale semiconductor modules list dram_open, dram_openfb (for 416 mapbga and 400 mapbga) these pins are the echo gating output and feedback pins used by the dram phy to bound a window around the dqs transition. for an application using a single dram device, these pins should be routed so that the trace length (dram_open + dram_openfb) = trace length (dram_sdclk0 + dram_sdqs0). for an application using two dram devices, they should be routed so that the trace length (dram_open + dram_openfb) = trace length (avg(dram_sdclk0+dram_sdclk1) + avg (dram_sdqs0_to_device0 + dram_sdqs0_to_device1)). this connection is required for lpddr1, lpddr2, and ddr2. for the i.mx50 pop package, these signals are connected on the substrate. dram_sdodt0 (for 416 mapbga and 400 mapbga), dram_sdodt1 (for 416 mapbga only) these pins are the on-die termination outputs from the i.mx50. for ddr2, these pins should be connected to the ddr2 dram odt pins. for lpddr1 and lpddr2, these pins should be left floating. note that both sdodt pins are removed on the 416 popbga package, and only sdodt0 exists on the 400 mapbga package. dram_calibration this pin is the zq calibration used to calibrate dram ron and odt. for lpddr2, this pin should be connected to ground through a 240 1% resistor. for ddr2 and lpddr1, this pin should be connected to ground through a 300 1% resistor. jtag_mod this input has an internal 100k pull-up, by default. note that jtag_mod is referenced as sjc_mod in the mcimx50 applications processor reference manual (mcimx50rm) - both names refer to the same signal. jtag_mod must be externally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ) is allowed. if jtag port is not needed, the internal pull-up can be disabled in order to reduce supply current to the pin. jtag_tck this input has an internal 100k pull-down. this pin is in the nvcc_jtag domain. jtag_tdi this input has an internal 47k pull-up to nvcc_jtag. this pin is in the nvcc_jtag domain. jtag_tdo this is a 3-state output with an internal gate keeper enable to prevent a floating condition. an external pull-up or pull-down resistor on jtag_tdo is detrimental and should be avoided. this pin is in the nvcc_jtag domain. jtag_tms this input has an internal 47k pull-up to nvcc_jtag. this pin is in the nvcc_jtag domain. jtag_trstb this input has an internal 47k pull-up to nvcc_jtag. this pin is in the nvcc_jtag domain. nc these signals are no connect (nc) and should be floated by the user. low_batt_gpio if the low_batt_gpio (uart4_txd) is asserted at power up, the i.mx50 will boot up at a lower arm clock frequency to reduce system power. the actual arm clock frequency used when low_batt_gpio is asserted is determined by the bt_lpb_freq[1:0] pins (220 mhz to 55.3 mhz). the polarity of the low_batt_gpio is active high by default, but may be set to active low by setting the low_batt_gpio_level otp bit. see the ?system boot? chapter of the reference manual for more details. note that this is not a dedicated pin: low_batt_gpio appears on the uart4_txd pin. pmic_stby_req this output may be driven high when the i.mx50 enters the stop mode to notify the pmic to enter its low power standby state. this output is in the nvcc_srtc domain. pmic_on_req this output from the i.mx50 can instruct the pmic to turn on when the i.mx50 only has nvcc_srtc power. this may be useful for an alarm application, as it allows the i.mx50 to turn off all blocks except for the rtc and then power on again at a specified time. this output is in the nvcc_srtc domain. table 5. special signal considerations (continued) signal name remarks
modules list i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 19 pmic_rdy this input may be used by a pmic to signal to the i.mx50 that the pmic supply outputs are at operating levels when resuming from stop mode. the pmic_rdy input is pin muxed on alt3 of the i2c3_scl pin and is in the nvcc_misc domain. pop_emmc_rst (416 popbga only) this pin is the pop emmc 4.4 reset pin. the customer may connect this on their pcb to any free gpio, or just leave floating for non-4.4 emmc. this pin does not connect to the i.mx50 die. pop_lpddr2_zq0/zq1 (416 popbga only) these pins connect to the pop lpddr2 dram zq pins and should be connected on the customer pcb to a 240 1% resistor to ground if used. these pins do not connect to the i.mx50 die. pop_lpddr2_1.8v (416 popbga only) these pins are the 1.8 v supply for the pop lpddr2 dram. these pins do not connect to the i.mx50 die. pop_nand_vcc (416 popbga only) this is the 3.3v i/o and memory supply for the pop emmc. note that most emmc can operate with a 1.8v i/o or a 3.3v i/o voltage. however, because we tied the emmc memory and i/o domains together, you can't use the 1.8 v i/o option for the pop emmc, only 3.3 v i/o. por_b this power-on reset input is a cold reset negative logic input that resets all modules and logic in the ic. the por_b pin should have an external 68 k pull-up to nvcc_reset and a 1 f capacitor to ground. note: the por_b input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. reset_in_b this warm reset negative logic input resets all modules and logic except for the following: ? test logic (jtag, iomuxc, dap) ?srtc ? cold reset logic of wdog?some wdog logic is only reset by por_b. see wdog chapter in the mcimx50 applications processor reference manual (mcimx50rm) for details. ssi_ext1_clk, ssi_ext2_clk the ssi_ext1_clk and ssi_ext2_clk outputs are recommended for generating a clock output from the i.mx50. use of the cko1 and cko2 clock outputs is not recommended, as the large number of combinational logic muxes on those signals will impact jitter and duty-cycle. note that these two clock outputs do not have dedicated pins: ssi_ext1_clk is iomux alt3 on the owire pin, and ssi_ext2_clk is iomux alt3 of the epito pin. test_mode test_mode is for freescale factory use only. this signal is internally connected to an on-chip pull-down device. the user must either float this signal or tie it to gnd. usb_h1_gpanaio, usb_otg_gpanaio these signals are reserved for freescale manufacturing use only. users should float these outputs. usb_h1_rrefext, usb_otg_rrefext these signals determine the reference current for the usb phy bandgap reference. an external 6.04 k 1% resistor to gnd is required. this resistor should be connected through a short (low impedance connection) and placed away from other noisy regions. if usb_h1 is not used, the h1 rrefext resistor may be eliminated and the pin left floating. if usb_otg is not used, the otg rrefext resistor may be eliminated and the pin left floating. table 5. special signal considerations (continued) signal name remarks
i.mx50 applications processors for consumer products, rev. 2 20 freescale semiconductor electrical characteristics 4 electrical characteristics this section provides the device and module-level electrical characteristics of the i.mx50 processor. note these electrical specifications are preliminary. these specifications are not fully tested or guaranteed at this early stage of the product life cycle. finalized specifications are published after thorough characterization and device qualifications have been completed. usb_h1_vbus, usb_otg_vbus these inputs are used by the i.mx50 to detect the presence and level of usb 5 v. if either vbus input pin is connected to an external usb connector, there is a possib ility that a fast 5 v edge rate during a cable attach could trigger the vbus input esd protection, which could result in damage to the i.mx50 silicon. to prevent this, the system should use some circuitry to prevent the 5 v edge rate from exceeding 5.25 v / 1 s. freescale recommends the use of a low pass filter consisting of 100 resistor in series and a 1 f capacitor close to the i.mx50 pin. in the case when the usb interface is connected on an on-board usb device (for example, 3g modem), the corresponding usb_vbus pin may be left floating. vref this pin is the dram mc reference voltage input. for lpddr2 and ddr2, this pin should be connected to ? of nvcc_emi_dram. for lpddr1, this pin should be left floating. the user may generate vref using a precision external resistor divider. use a 1 k 0.5% resistor to gnd and a 1 k 0.5% resistor to nvcc_emi_dram. shunt each resistor with a closely-mounted 0.1 f capacitor. wdog_b this output can be used to reset the system pmic when the i.mx50 processor is locked up. this output is in the nvcc_misc domain. wdog_rst_b_deb this output may be used to drive out the internal system reset signal to the system reset controller. this is only intended for debug purposes. xtal/extal these pins are the 24 mhz crystal driver as well as the external 24 mhz clock input. if using these pins to directly drive a 24 mhz crystal: ? the user should tie a 24 mhz fundamental-mode crystal across xtal and extal. ? the crystal must be rated for a maximum drive level of 100 w or higher. ? the recommended crystal esr (equivalent series resistance) is 80 or less. if using these pins as a clock input from an external 24 mhz oscillator: ? the crystal may be eliminated and extal driven directly driven by the external oscillator. the clock signal level on extal must swing from nvcc_srtc to gnd. ? in this configuration, the xtal pin must be floated and the cosc_en bit (bit 12 in the ccr register in the clock control module) must be cleared to put the on-chip oscillator circuit in bypass mode which allows extal to be externally driven. ? note there are strict jitter requirements if using an external oscillator in a usb application: < 50 ps peak-to-peak below 1.2 mhz and < 100 ps peak-to-peak above 1.2 mhz for the usb phy. table 5. special signal considerations (continued) signal name remarks
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 21 4.1 chip-level conditions this section provides the chip-level electrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. 4.1.1 absolute maximum ratings caution stresses beyond those listed under table 7 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in table 11 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. table 6. i.mx50 chip-level conditions for these characteristics, see topic appears ? absolute maximum ratings on page 21 13 x 13 mm mapbga package thermal resistance data on page 22 13 x 13 mm popbga package thermal resistance data on page 23 17 x 17 mm mapbga package thermal resistance data on page 23 operating ranges on page 24 operating frequencies on page 26 supply current on page 26 table 7. absolute maximum ratings parameter description symbol min max unit peripheral core supply voltage vcc ?0.3 1.5 v arm core supply voltage vddgp ?0.3 1.35 v bandgap and 480 mhz pll supply vdd3p0 ?0.5 3.6 v pll digital supplies vdd1p2 ?0.3 1.35 v pll analog supplies vdd1p8 ?0.3 2.25 v efuse, 24 mhz oscillator, 32 khz oscillator mux supply vdd2p5 ?0.5 2.85 v memory array supply vdda/vddal1 ?0.5 1.35 v supply voltage (hvio) supplies denoted as i/o supply ?0.5 3.6 v supply voltage (gpio, lvio) supplies denoted as i/o supply ?0.5 3.3 v input/output voltage range v in /v out ?0.5 ovdd + 0.3 1 v usb vbus vbus v dc transient (t<30ms, duty cycle < 0.05%) ? ? 6.00 7.00
i.mx50 applications processors for consumer products, rev. 2 22 freescale semiconductor electrical characteristics 4.1.2 thermal resistance data 4.1.2.1 13 x 13 mm mapbga package thermal resistance data table 8 provides thermal resistance data for a 13 x 13 mm mapbga package. esd damage immunity: v esd v human body model (hbm) charge device model (cdm) ? ? 2000 500 storage temperature range t storage ?40 125 o c 1 the term ovdd in this section refers to the associated supply rail of an input or output. the maximum range can be superseded by the dc tables. table 8. 13 x 13 mm mapbga package thermal resistance data rating board symbol value unit junction to ambient (natural convection) 1, 2 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per jedec jesd51-2 with the single layer board horizontal. the thermal test board meets jesd51-9 specification. single layer board (1s) r ja 51 c/w junction to ambient (natural convection) 1, 2, 3 3 per jedec jesd51-6 with the board horizontal. four layer board (2s2p) r ja 28 c/w junction to ambient (at 200 ft/min) 1, 3 single layer board (1s) r jma 40 c/w junction to ambient (at 200 ft/min) 1, 3 four layer board (2s2p) r jma 24 c/w junction to board 4 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. ? r jb 14 c/w junction to case 5 5 thermal resistance between the die and the case top surface as measured by using the cold plate method (mil spec-883 method 1012.1). ? r jc 9c/w junction to package top (natural convection) 6 6 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. ? jt 2c/w table 7. absolute maximum ratings (continued) parameter description symbol min max unit
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 23 4.1.2.2 13 x 13 mm popbga package thermal resistance data table 9 provides thermal resistance data for a 13 x 13 mm popbga package. 4.1.2.3 17 x 17 mm mapbga package thermal resistance data table 10 provides thermal resistance data for a 17 x 17 mm mapbga package. table 9. 13 x 13 mm popbga package thermal resistance data rating board symbol value unit junction to ambient (natural convection) 1, 2 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per jedec jesd51-2 with the single layer board horizontal. the thermal test board meets jesd51-9 specification. single layer board (1s) r ja 57 c/w junction to ambient (natural convection) 1, 2, 3 3 per jedec jesd51-6 with the board horizontal. four layer board (2s2p) r ja 31 c/w junction to ambient (at 200 ft/min) 1, 3 single layer board (1s) r jma 46 c/w junction to ambient (at 200 ft/min) 1, 3 four layer board (2s2p) r jma 28 c/w junction to board 4 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. ? r jb 18 c/w junction to case 5 5 thermal resistance between the die and the case top surface as measured by using the cold plate method (mil spec-883 method 1012.1). ? r jc 6c/w junction to package top (natural convection) 6 6 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. ? jt 2c/w table 10. 17 x 17 mm mapbga package thermal resistance data rating board symbol value unit junction to ambient (natural convection) 1, 2 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per jedec jesd51-2 with the single layer board horizontal. the thermal test board meets jesd51-9 specification. single layer board (1s) r ja 53 c/w junction to ambient (natural convection) 1, 2, 3 four layer board (2s2p) r ja 30 c/w junction to ambient (at 200 ft/min) 1, 3 single layer board (1s) r jma 44 c/w junction to ambient (at 200 ft/min) 1, 3 four layer board (2s2p) r jma 26 c/w junction to board 4 ? r jb 19 c/w junction to case 5 ? r jc 8c/w junction to package top (natural convection) 6 ? jt 2c/w
i.mx50 applications processors for consumer products, rev. 2 24 freescale semiconductor electrical characteristics 4.1.3 operating ranges table 11 provides the operating ranges of the i.mx50 processor. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by using the cold plate method (mil spec-883 method 1012.1). 6 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 11. i.mx50 operating ranges symbol parameter minimum 1 nominal 2 maximum 1 unit vddgp arm core supply voltage 400 < f arm 800 mhz 0.95 1.05 1.15 v arm core supply voltage 167 < f arm 400 mhz 0.85 0.95 1.15 v arm core supply voltage 24 f arm 167 mhz 0.8 0.9 1.15 v arm core supply voltage stop mode 0.75 0.85 1.15 v vcc peripheral supply voltage low performance mode (lpm). the ddr clock rate is 24 mhz. 0.9 0.95 1.275 v peripheral supply voltage reduced performance mode (rpm). the ddr clock rate is 100 mhz. 1 3 1.05 1.275 v peripheral supply voltage high performance mode (hpm). the clock frequencies are derived from ahb bus using 133 mhz and axi bus using 266 mhz (as needed). the ddr clock rate is 200 mhz. 1.175 1.225 1.275 v vdda/vddal1 memory arrays voltage?run mode 1.15 1.20 1.275 v memory arrays voltage?stop mode 0.9 3 0.95 1.275 v vdd3p0 bandgap and 480 mhz pll supply 2.7 3.0 3.3 v vdd2p5 efuse, 24 mhz oscillator, 32 khz oscillator mux supply 2.375 2.5 2.625 v vdd1p2 pll digital supplies 1.15 1.2 1.32 v vdd1p8 pll analog supplies 1.75 1.8 1.95 v nvcc_jtag gpio digital power supplies 1.65 1.875 or 2.775 3.1 v nvcc_emi_dram ddr supply ddr2/lpddr1 range 1.71 1.8 1.95 v ddr supply lpddr2 range 1.14 1.2 1.3 v
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 25 vref dram reference voltage input 1/2 nvcc_e mi_dram vddo25 emi pad predriver supply 2.375 2.5 2.625 v nvcc_nandf nvcc_sd1 nvcc_sd2 nvcc_keypad nvcc_eim nvcc_epdc nvcc_lcd nvcc_misc nvcc_spi nvcc_ssi nvcc_uart high voltage i/o (hvio) supplies hvio_l hvio_h 1.65 2.7 1.875 3.0 1.95 3.3 v nvcc_srtc srtc core and i/o supply (lvio) 1.1 1.2 1.3 v nvcc_reset lvio 1.65 1.875 or 2.775 3.1 v usb_h1_vdda25 usb_otg_vdda25 4 usb_phy analog supply 2.25 2.5 2.75 v usb_h1_vdda33 usb_otg_vdda33 5 usb phy i/o analog supply 3.0 3.3 3.6 v vbus see ta ble 7 and ta b l e 7 7 for details. this is not a power supply. ?? ?? t a ambient temperature, consumer 0 ? 70 o c t a extended ambient temperature, consumer -20 ? 70 o c t j junction temperature, consumer 0 ? 90 o c t j extended junction temperature, consumer -20 ? 90 o c 1 voltage at the package power supply contact must be maintained between the minimum and maximum voltages. the design must allow for supply tolerances and system voltage drops. 2 the nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mv. use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. 3 vcc minimum voltage is 1.02 v for extended temperature (-20 c) devices. 4 usb_otg_vdda25 and usb_h1_vdda25 are shorted t ogether on the 416 mapbga and 416 popbga package substrates. 5 usb_otg_vdda33 and usb_h1_vdda33 are shorted t ogether on the 416 mapbga and 416 popbga package substrates. table 11. i.mx50 operating ranges (continued) symbol parameter minimum 1 nominal 2 maximum 1 unit
i.mx50 applications processors for consumer products, rev. 2 26 freescale semiconductor electrical characteristics 4.1.4 operating frequencies table 12 shows the interface frequency requirements. 4.1.5 supply current table 13 shows the run mode current consumption of the i.mx50. table 12. interface frequency parameter description symbol min max unit jtag: tck operating frequency f tck see ta b l e 6 3 mhz ckil: operating frequency f ckil 32.768 1 1 generated internally or applied externally. khz ckih: operating frequency f ckih see ta b l e 3 7 mhz xtal oscillator f xtal 22 27 mhz table 13. e-fuse supply current description symbol min typ max unit efuse program current 1 vdd2p5 current is required to program one efuse bit. 1 the current i program is only required during program time (t program ). i program ?4055ma
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 27 table 14 shows the maximum supply current consumption of the i.mx50 for pmic specification purposes. 4.1.5.1 conditions for stop mode current and power consumption ? arm core in stop mode and power gated ? vddgp, vcc, and vdda/vddal1 voltages at suspend levels ? vdd3p0, vdd2p5, vdd1p8, and vdd1p2 powered off ? usb_vdda25 and usb_vdda33 powered off ? all other supply voltages at nominal levels table 14. maximum supply current consumption condition supply voltage (v) current (ma) power (mw) ?t a = 70 c ? arm core in run mode ? arm clk = 800 mhz ? sys clk = 266 mhz ? ahb clk = 133 mhz ? ddr clk = 266 mhz ? all voltages operating at maximum levels ? external (mhz) crystal and on-chip oscillator enabled ? all modules enabled vddgp 1.15 628 723 vcc 1.275 185 236 vdda/vddal1 1.275 40 51 vdd1p2 1.3 5.92 7.70 vdd1p8 1.95 1.53 2.99 vdd2p5 1 1 during efuse programming, the maximum current on vdd2p5 will exceed these values. see ta b l e 1 3 for the maximum vdd2p5 current during efuse programming. 2.75 1.13 3.11 vdd3p0 3.3 1.61 5.32 nvcc_emi_dram 1.95 8.3 16.17 vdd_dcdci 1.95 0.021 0.041 usb_otg_vdda33 + usb_h1_vdda33 3.6 10.8 38.8 vddo25 + usb_otg_vdda25 + usb_h1_vdda25 2.75 12.45 34.239 nvcc_reset 3.1 0.226 0.701 nvcc_srtc 1.3 0.0035 0.0045 to t a l 1 1 2 0 table 15. stop mode current and power consumption 1 1 the typical power, at ta = 25 c, will be < 1 mw, including all supplies. total max power, at ta=25 c, will not exceed 2.5 mw, including all supplies. supply voltage (v) current (ma) typical, t a = 25 cmax, t a = 25 c vddgp 0.85 0.057 0.198 vcc 0.95 0.544 1.890 vdda/vddal1 0.95 0.071 0.247
i.mx50 applications processors for consumer products, rev. 2 28 freescale semiconductor electrical characteristics ? external (mhz) crystal and on-chip oscillator disabled ? ckil input on with 32 khz signal present ? all plls off, all ccm- generated clocks off ? all modules disabled ? no external resistive loads that cause current 4.1.6 usb-oh-1 (otg + 1 host port) current consumption table 16 shows the usb interface current consumption. 4.2 supply power-up/power-down requirements and restrictions the system design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the devi ce. any deviation from these sequences can result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the i.mx50 processor (worst-case scenario) table 16. usb interface current consumption parameter conditions typical @ 25 c max unit analog supply 3.3 v usb_h1_vdda33 usb_otg_vdda33 full speed rx 5.5 6 ma tx 7 8 high speed rx 5 6 tx 5 6 analog supply 2.5 v usb_h1_vdda25 usb_otg_vdda25 full speed rx 6.5 7 ma tx 6.5 7 high speed rx 12 13 tx 21 22 digital supply vcc (1.2 v) full speed rx 6 7 ma tx 6 7 high speed rx 6 7 tx 6 7
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 29 4.2.1 power-up sequence figure 2 shows the power-up sequence. figure 2. power-up sequence note 1) the por_b input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. 2) no power-up sequence dependencies exist between the supplies shown shaded in gray. 4.2.2 power-down sequence the power-down sequence is recommended to be the opposite of the power-up sequence. in other words, the same power supply constraints exist while powering off as while powering on. 4.2.3 resume sequence when the i.mx50 is resuming from stop mode, ther e are some special sequencing considerations. the resume timing is determined by the following internal counters: 1. stby_count. this register is in the ccm block and may be set to a maximum of 16 x 32 khz cycles, or 500 sec.
i.mx50 applications processors for consumer products, rev. 2 30 freescale semiconductor electrical characteristics 2. oscnt. this register is in the ccm block a nd may be set to a maximum of 256 x 32 khz cycles, or 8 msec. this counter is intended to give the 24mhz clock time to start up and stabilize. if the pmic_rdy input is used and bypass_pmic_vfunctional_ready = 0, the i.mx50 will wait for stby_count cycles after pmic_stby_req negation before checking pmic_rdy status. once the stby_count has expired and the pmic_rdy signal has been asserted, the oscnt counter begins and the 24mhz oscillator is powered up. after oscnt expires the processor will enter run mode. if the pmic_rdy input is not used, the processor will attempt to start the 24 mhz oscillator after stby_count expires. so at a minimum, all the supplies necessary to start up the 24 mhz oscillator need to be powered before stby_count expires: nvcc_srtc,vdd1p2, vdd1p8, vdd2p5, vdd3p0. after stby_count expires, the oscnt counter begins and the 24 mhz oscillator is powered up. after oscnt expires the processor will enter run mode, so all other supplies need to be at the appropriate operating levels before oscnt expires. 4.3 i/o dc parameters this section includes the dc parameters of the following i/o types: ? general purpose i/o and high-speed general purpose i/o (gpio) ? double data rate 2 (ddr2) ? low power double data rate 2 (lpddr2) ? low power double data rate 1(lpddr1) ? low voltage i/o (lvio) ? high voltage i/o (hvio) ? secure digital host controllers (esdhcv2 and esdhcv3) ? usb-otg and usb host ports note the term ovdd in this section refers to the associated supply rail of an input or output. 4.3.1 gpio i/o dc parameters the parameters in table 17 are guaranteed per the operating ranges in table 11 , unless otherwise noted. table 17. gpio dc electrical characteristics dc electrical characteristics symbol test conditions min typ max units high-level output voltage voh ioh=-1ma ioh=spec?ed drive ovdd-0.15 0.8*ovdd ?? v low-level output voltage vol iol=1ma iol=specified drive ? ? 0.15 0.2*ovdd v
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 31 high-level output current (1.1-1.3v ovdd) i ioh voh=0.8*ovdd low drive medium drive high drive max drive -0.85 -1.7 -2.5 -3.4 ?? ma low-level output current (1.1-1.3v ovdd) i iol vol=0.2*ovdd low drive medium drive high drive max drive 0.9 1.9 2.9 3.8 ?? ma high-level output current (1.65-3.1v ovdd) i ioh voh=0.8*ovdd low drive medium drive high drive max drive -2.1 -4.2 -6.3 -8.4 ?? ma low-level output current (1.65-3.1v ovdd) i iol vol=0.2*ovdd low drive medium drive high drive max drive 2.1 4.2 6.3 8.4 ?? ma high-level dc input voltage 1 vih ? 0.7*ovdd ? ovdd v low-level dc input voltage vil ? 0v ? 0.3*ovdd v input hysteresis vhys ovdd=1.875 ovdd=2.775 0.25 0.34 0.45 ?v schmitt trigger vt+ 2 vt+ ? 0.5*ovdd ? ? v schmitt trigger vt- vt- ? ? ? 0.5*ovdd v pull-up resistor (22 k pu) rpu vi=ovdd/2 20 24 28 k pull-up resistor (47 k pu) rpu vi=ovdd/2 43 51 59 k pull-up resistor (100 k pu) rpu vi=ovdd/2 91 108 125 k pull-down resistor (100 k pd) rpd vi=ovdd/2 91 108 126 k input current (no pull-up/down) iin vi = 0 vi=ovdd ? 1.7 250 120 na input current (22 k pu) iin vi = 0 vi=ovdd ? ? 161 0.12 a input current (47 k pu) iin vi = 0 vi=ovdd ??76 0.12 a input current (100 k pu) iin vi = 0 vi=ovdd ??36 0.12 a table 17. gpio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min typ max units
i.mx50 applications processors for consumer products, rev. 2 32 freescale semiconductor electrical characteristics 4.3.2 ddr2 i/o dc parameters the ddr2 interface fully complies with jesd79-2e ddr2 jedec standard release april, 2008. the jedec lpddr2 specification (jesd209_2b) supersedes any specification in this document. the parameters in table 18 are guaranteed per the operating ranges in table 11 , unless otherwise noted. input current (100 k pd) iin vi = 0 vi=ovdd ? ? 0.25 36 a external pull-up / pull-down resistor required to overdrive internal keeper rext ? ? ? 47 k 1 to maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current d c level through to the target dc level, vil or vih. monotonic input transition time is from 0.1ns to 1s. vil and vih do not apply when hysteresis is enabled. 2 hysteresis of 250 mv is guaranteed overall operating conditions when hysteresis is enabled. table 18. ddr2 dc electrical characteristics dc electrical characteristics symbol test conditions min typ max units high-level output voltage voh ? 0.9*ovdd ? ? v low-level output voltage vol ? ? ? 0.1*ovdd v output min source current 1 1 ovdd=1.7 v; vout=1.42 v. (vout-ovdd)/ioh must be less than 21 for values of vout between ovdd and ovdd-0.28 v. ioh(dc) ? -7.5 ? ? ma output min sink current 2 2 ovdd=1.7 v; vout=280 mv. vout/iol must be less than 21 for values of vout between 0 v and 280 mv. iol(dc) ? 7.5 ? ? ma input reference voltage vref ? 0.49*ovdd 0.5*ovdd 0.51*ovdd ? dc input high voltage (data pins) vihd(dc) ? vref+0.125 ? ovdd+0.3 v dc input low voltage (data pins) vild(dc) ? -0.3 ? vref-0.125 v dc input voltage 3 (clk pins) 3 vin(dc) specifies the allowable dc excursion of each differential input. vin(dc) ? -0.3 ? ovdd+0.3 v dc differential input voltage 4 4 vid(dc) specifies the input differential voltage |vtr-vcp| required for switching, where vtr is the ?pure? input level and vcp is the ?complementary? input level. the minimum value is equal to vih(dc) - vil(dc). vid(dc) ? 0.25 ? ovdd+0.6 v termination voltage 5 5 vtt is expected to track ovdd/2. vtt ? vref-0.04 vref vref+0.04 ? input current 6 (no pull-up/down) 6 typ condition: typ model, 1.8 v, and 25 c. max condition: bcs model, 1.9 v, and 125 c. min condition: wcs model, 1.7 v, and -40 c. iin vi = 0 vi=ovdd ?0.07 2 5 360 na tri-state i/o supply current 6 icc-ovdd vi = ovdd or 0 ? 2.3 480 na tri-state 2.5v predrivers supply current 6 icc-vdd2p5 vi = ovdd or 0 ? 6.4 750 na tri-state core supply current 6 icc-vddi vi = ovdd or 0 ? 3.1 720 na table 17. gpio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min typ max units
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 33 4.3.3 low power ddr2 i/o dc parameters the lpddr2 interface fully complies with jedec standard release april, 2008. the parameters in table 19 are guaranteed per the operating ranges in table 11 , unless otherwise noted. 4.3.4 low power ddr1 i/o dc parameters the lpddr1 interface fully complies with jedec st andard release april, 2008. the parameters in table 20 are guaranteed per the operating ranges in table 11 , unless otherwise noted. table 19. lpddr2 i/o dc electrical parameters dc electrical characteristics symbol test conditions min typ max units high-level output voltage voh ? 0.9*ovdd ? ? v low-level output voltage vol ? ? ? 0.1*ovdd v input reference voltage vref ? 0.49*ovdd 0.5*ovdd 0.51*ovdd ? dc input high voltage vih(dc) ? vref+0.13 ? ovdd v dc input low voltage vil(dc) ? ovss ? vref-0.13 v differential input logic high 1 1 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. vih(diff) ? 0.26 ? ? v differential input logic low 1 vil(diff) ? ? ? -0.26 v input current (no pull-up/down) iin vi = 0 vi=ovdd ?0.02 1.5 12.8 290 na tri-state i/o supply current 2 2 typ condition: typ model, 1.2v, and 25 c. max condition: bcs model, 1.3v, and 125 c. min condition: wcs model, 1.14v, and -40 c. icc-ovdd vi = ovdd or 0 ? 1.85 400 na tri-state 2.5 v predrivers supply current 2 icc-vdd2p5 vi = ovdd or 0 ? 5 700 na tri-state core supply current 2 icc-vddi vi = ovdd or 0 ? 3 700 na pullup/pulldown impedance mismatch 2 ?? -15?+15% 240 unit calibration resolution ? ? ? ? 10 table 20. lpddr1 mode dc electrical characteristics dc electrical characteristics symbol test conditions min typ max units high-level output voltage voh ioh=-0.1ma 0.9*ovdd ? ? v low-level output voltage vol iol=0.1ma ? ? 0.1*ovdd v dc input high voltage (data pins) vihd(dc) ? 0.7*ovdd ? ovdd+0.3 v dc input low voltage (data pins) vild(dc) ? -0.3 ? 0.3*ovdd v dc input voltage 1 (clk pins) vin(dc) ? -0.3 ? ovdd+0.3 v dc input differential voltage 2 vid(dc) ? 0.4*ovdd ? ovdd+0.6 v input current 3 (no pull-up/down) iin vi = 0 vi=ovdd ?0.07 2 5 360 na tri-state i/o supply current 3 icc-ovdd vi = ovdd or 0 ? 2.3 480 na tri-state 2.5v predrivers supply current 3 icc-vdd2 p5 vi = ovdd or 0 ? 5.3 680 na tri-state core supply current 3 icc-vddi vi = ovdd or 0 ? 3.1 720 na
i.mx50 applications processors for consumer products, rev. 2 34 freescale semiconductor electrical characteristics 4.3.5 low voltage i/o (lvio) dc parameters the parameters in table 21 are guaranteed per the operating ranges in table 11 , unless otherwise noted. 1 vin(dc) specifies the allowable dc excursion of each differential input. 2 vid(dc) specifies the input differential voltage |vtr-vcp| required for switching, where vtr is the ?pure? input level and vcp is the ?complementary? input level. the minimum value is equal to vih(dc) - vil(dc). 3 typ condition: typ model, 1.8 v, and 25 c. max condition: bcs model, 1.9 v, and 105 c. min condition: wcs model, 1.7 v, and -20 c. table 21. lvio dc electrical characteristics dc electrical characteristics symbol test conditions min typ max units high-level output voltage voh ioh=-1ma ioh=spec?ed drive ovdd-0.15 0.8*ovdd ?? v low-level output voltage vol iol=1ma iol=specified drive ? ? 0.15 0.2*ovdd v high-level output current i ioh voh=0.8*ovdd low drive medium drive high drive max drive -2.1 -4.2 -6.3 -8.4 ?? ma low-level output current i iol vol=0.2*ovdd low drive medium drive high drive max drive 2.1 4.2 6.3 8.4 ?? ma high-level dc input voltage 1 vih ? 0.7*ovdd ? ovdd v low-level dc input voltage vil ? 0v ? 0.3*ovdd v input hysteresis vhys ovdd=1.875 ovdd=2.775 0.35 0.62 1.27 ?v schmitt trigger vt+ 2 vt+ ? 0.5*ovdd ? ? v schmitt trigger vt- vt- ? ? ? 0.5*ovdd v pull-up resistor (22 k pu) rpu vi=ovdd/2 20 24 28 k pull-up resistor (47 k pu) rpu vi=ovdd/2 43 51 59 k pull-up resistor (100 k pu) rpu vi=ovdd/2 91 108 125 k pull-down resistor (100 k pd) rpd vi=ovdd/2 91 108 126 k input current (no pull-up/down) iin vi = 0 vi=ovdd ?1.7250 120 na input current (22 k pu) iin vi = 0 vi=ovdd ??161 0.12 a input current (47 k pu) iin vi = 0 vi=ovdd ??76 0.12 a input current (100 k pu) iin vi = 0 vi=ovdd ??36 0.12 a
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 35 4.3.6 high voltage i/o (hvio) dc parameters table 22 shows the hvio dc electrical operating conditions. the parameters are guaranteed per the operating ranges in table 11 , unless otherwise noted. input current (100 k pd) iin vi = 0 vi=ovdd ? ? 0.25 36 a external pull-up / pull-down resistor required to overdrive internal keeper rext ? ? ? 47 k 1 to maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current d c level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vil and vih do not app ly when hysteresis is enabled. 2 hysteresis of 350 mv is guaranteed over all operating conditions when hysteresis is enabled. table 22. hvio dc electrical characteristics dc electrical characteristics symbol test conditions min typ max units high-level output voltage voh ioh=-1ma ioh=spec?ed drive ovdd-0.15 0.8*ovdd ?? v low-level output voltage vol iol=1ma iol=specified drive ? ? 0.15 0.2*ovdd v high-level output current, low voltage mode ioh_lv voh=0.8*ovdd low drive medium drive high drive -2.2 -4.4 -6.6 ?? ma high-level output current, high voltage mode ioh_hv vol=0.8*ovdd low drive medium drive high drive -5.1 -10.2 -15.3 ?? ma low-level output current, low voltage mode iol_lv voh=0.2*ovdd low drive medium drive high drive 2.2 4.4 6.6 ?? ma low-level output current, high voltage mode iol_hv voh=0.2*ovdd low drive medium drive high drive 5.1 10.2 15.3 ?? ma high-level dc input voltage 1 vih ? 0.7*ovdd ? ovdd v low-level dc input voltage vil ? 0v ? 0.3*ovdd v input hysteresis vhys ovdd=1.875 ovdd=3.0 0.25 0.36 0.80 ?v schmitt trigger vt+ 2 vt+ ? 0.5*ovdd ? ? v schmitt trigger vt- vt- ? ? ? 0.5*ovdd v table 21. lvio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min typ max units
i.mx50 applications processors for consumer products, rev. 2 36 freescale semiconductor electrical characteristics 4.4 output buffer impedance characteristics this section defines the i/o impedance parameters of the i.mx50 processor. pull-up resistor (22 k pu) rpu vi=ovdd/2 22 29 71 k pull-up resistor (47 k pu) rpu vi=ovdd/2 43 59 148 k pull-up resistor (100 k pu) rpu vi=ovdd/2 46 62 156 k pull-down resistor (100 k pd) rpd vi=ovdd/2 53 77 256 k input current (no pull-up/down) iin vi = 0 vi=ovdd ? 2.8 470 50 na input current (22 k pu) iin vi = 0 vi=ovdd ? ? 153 0.05 a input current (47 k pu) iin vi = 0 vi=ovdd ??77 0.05 a input current (100 k pu) iin vi = 0 vi=ovdd ??73 0.05 a input current (100 k pd) iin vi = 0 vi=ovdd ? ? 0.47 63 a high-level output current, high voltage mode ioh_hv vol=0.8*ovdd low drive medium drive high drive -5.1 -10.2 -15.3 ?? ma external pull-up / pull-down resistor required to overdrive internal keeper rext ? ? ? 2.5 k 1 to maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current d c level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vil and vih do not app ly when hysteresis is enabled. 2 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. table 22. hvio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min typ max units
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 37 4.4.1 gpio output buffer impedance table 23 shows the gpio output buffer impedance of the i.mx50 processor. 4.4.2 lvio output buffer impedance table 24 shows the lvio output buffer impedance of the i.mx50 processor. table 23. gpio output buffer impedance parameter symbol test conditions min typ max unit ovdd 2.775 v ovdd 1.875v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 80 40 27 20 104 52 35 26 150 75 51 38 250 125 83 62 output driver impedance rpd low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 64 32 21 16 88 44 30 22 134 66 44 34 243 122 81 61 table 24. lvio output buffer impedance parameter symbol test conditions min typ max unit ovdd 2.775 v ovdd 1.875v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 80 40 27 20 104 52 35 26 150 75 51 38 250 125 83 62 output driver impedance rpd low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 64 32 21 16 88 44 30 22 134 66 44 34 243 122 81 61
i.mx50 applications processors for consumer products, rev. 2 38 freescale semiconductor electrical characteristics 4.4.3 hvio output buffer impedance table 25 shows the hvio output buffer impedance of the i.mx50 processor. note output driver impedance is measured with long transmission line of impedance ztl attached to i/o pad and incident wave launched into transmission line. rpu/rpd and ztl form a voltage divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 3 ). table 25. hvio output buffer impedance parameter symbol test conditions min typ max unit ovdd 1.95 v ovdd 3.3 v ovdd 1.875 v ovdd 3.30v ovdd 1.65 v ovdd 2.68 v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 113.5 56.2 37.8 103.8 51.9 35.1 130.6 66 45.9 133 69.2 41 219.4 109.7 73.1 212.2 111.1 71.8 output driver impedance rpd low drive strength, ztl =1 50 medium drive strength, ztl = 75 high drive strength, ztl = 50 78.5 39.7 26.8 70 34.5 23 113.6 56.8 38.3 102 50 33.3 230.8 115.4 76.9 179.5 89.8 60.7
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 39 figure 3. impedance matching load for measurement ipp_do cload = 1p ztl w, l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) 0 u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd ? vref1 vref1 ztl rpd = ztl vref2 vovdd ? vref2 vref1 vref2
i.mx50 applications processors for consumer products, rev. 2 40 freescale semiconductor electrical characteristics 4.5 i/o ac parameters the load circuit and output transition time waveforms are shown in figure 4 and figure 5 . the ac electrical characteristics for slow and fast i/o are presented in the table 26 and table 27 , respectively. note that the fast or slow i/o behavior is determined by the appropriate control bit in the iomux control registers. figure 4. load circuit for output figure 5. output transition time waveform 4.5.1 gpio i/o slow ac parameters table 26 shows the ac parameters for gpio slow i/o. table 26. gpio i/o slow ac parameters parameter symbol test condition min typ max unit output pad transition times (max drive) tr, tf 15 pf 35 pf 1.91/1.52 3.07/2.65 ns output pad transition times (high drive) tr, tf 15 pf 35 pf 2.22/1.81 3.81/3.42 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf 2.88/2.42 5.43/5.02 ns output pad transition times (low drive) tr, tf 15 pf 35 pf 4.94/4.50 10.55/9.70 ns output pad slew rate (max drive) 1 tps 15 pf 35 pf 0.5/0.65 0.32/0.37 v/ns output pad slew rate (high drive) tps 15 pf 35 pf 0.43/0.54 0.26/0.41 v/ns output pad slew rate (medium drive) tps 15 pf 35 pf 0.34/0.41 0.18/0.2 v/ns output pad slew rate (low drive) tps 15 pf 35 pf 0.20/0.22 0.09/0.1 v/ns output pad di/dt (max drive) tdit 30 ma/ns test point from output cl cl includes package, probe and fixture capacitance under test 0v nvcc 20% 80% 80% 20% tr tf output (at i/o)
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 41 4.5.2 gpio i/o fast ac parameters table 27 shows the ac parameters for gpio fast i/o. output pad di/dt (high drive) tdit 23 ma/ns output pad di/dt (medium drive) tdit 15 ma/ns output pad di/dt (low drive) tdit 7 ma/ns input transition times 2 trm 25 ns 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. table 27. gpio i/o fast ac parameters parameter symbol test condition min typ max unit output pad transition times (max drive) tr, tf 15 pf 35 pf 1.45/1.24 2.76/2.54 ns output pad transition times (high drive) tr, tf 15 pf 35 pf 1.81/1.59 3.57/3.33 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf 2.54/2.29 5.25/5.01 ns output pad transition times (low drive) tr, tf 15 pf 35 pf 4.82/4.50 10.54/9.95 ns output pad slew rate (max drive) 1 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. tps 15 pf 35 pf 0.69/0.78 0.36/0.39 v/ns output pad slew rate (high drive) tps 15 pf 35 pf 0.55/0.62 0.28/0.30 v/ns output pad slew rate (medium drive) tps 15 pf 35 pf 0.39/0.44 0.19/0.20 v/ns output pad slew rate (low drive) tps 15 pf 35 pf 0.21/0.22 0.09/0.1 v/ns output pad di/dt (max drive) tdit ? ? ? 70 ma/ns output pad di/dt (high drive) tdit ? ? ? 53 ma/ns output pad di/dt (medium drive) tdit ? ? ? 35 ma/ns output pad di/dt (low drive) tdit ? ? ? 18 ma/ns input transition times 2 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. trm ? ? ? 25 ns table 26. gpio i/o slow ac parameters (continued) parameter symbol test condition min typ max unit
i.mx50 applications processors for consumer products, rev. 2 42 freescale semiconductor electrical characteristics 4.5.3 lvio i/o slow ac parameters table 26 shows the ac parameters for lvio slow i/o. table 28. lvio i/o slow ac parameters parameter symbol test condition min typ max unit output pad transition times (max drive) tr, tf 15 pf 35 pf 1.97/1.57 3.12/2.70 ns output pad transition times (high drive) tr, tf 15 pf 35 pf 2.29/1.87 3.79/3.44 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf 2.93/2.48 5.42/4.98 ns output pad transition times (low drive) tr, tf 15 pf 35 pf 4.92/4.57 10.64/9.85 ns output pad slew rate (max drive) 1 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. tps 15 pf 35 pf 0.50/0.63 0.32/0.37 v/ns output pad slew rate (high drive) tps 15 pf 35 pf 0.43/0.53 0.26/0.29 v/ns output pad slew rate (medium drive) tps 15 pf 35 pf 0.34/0.40 0.18/0.20 v/ns output pad slew rate (low drive) tps 15 pf 35 pf 0.20/0.22 0.09/0.10 v/ns output pad di/dt (max drive) tdit 30 ma/ns output pad di/dt (high drive) tdit 24 ma/ns output pad di/dt (medium drive) tdit 16 ma/ns output pad di/dt (low drive) tdit 8 ma/ns input transition times 2 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. trm 25 ns
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 43 4.5.4 lvio i/o fast ac parameters table 29 shows the ac parameters for lvio fast i/o. 4.5.5 hvio i/o low voltage (1.8 v) ac parameters table 26 shows the ac parameters for hvio i/o low voltage (1.8 v). table 29. lvio i/o fast ac parameters parameter symbol test condition min typ max unit output pad transition times (max drive) tr, tf 15 pf 35 pf 1.44/1.27 2.78/2.56 ns output pad transition times (high drive) tr, tf 15 pf 35 pf 1.80/1.61 3.59/3.34 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf 2.55/2.28 5.32/5.01 ns output pad transition times (low drive) tr, tf 15 pf 35 pf 4.74/4.59 10.59/10.21 ns output pad slew rate (max drive) 1 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. tps 15 pf 35 pf 0.69/0.78 0.36/0.39 v/ns output pad slew rate (high drive) tps 15 pf 35 pf 0.55/0.61 0.28/0.30 v/ns output pad slew rate (medium drive) tps 15 pf 35 pf 0.39/0.44 0.19/0.20 v/ns output pad slew rate (low drive) tps 15 pf 35 pf 0.21/0.22 0.09/0.10 v/ns output pad di/dt (max drive) tdit ? ? ? 70 ma/ns output pad di/dt (high drive) tdit ? ? ? 54 ma/ns output pad di/dt (medium drive) tdit ? ? ? 35 ma/ns output pad di/dt (low drive) tdit ? ? ? 18 ma/ns input transition times 2 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. trm ? ? ? 25 ns table 30. hvio i/o low voltage (1.8 v) ac parameters parameter symbol test condition min typ max unit output pad transition times (high drive) tr, tf 15 pf 35 pf 1.82/1.97 3.39/3.57 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf 2.48/2.62 4.95/5.14 ns output pad transition times (low drive) tr, tf 15 pf 35 pf 4.57/4.77 9.60/9.91 ns
i.mx50 applications processors for consumer products, rev. 2 44 freescale semiconductor electrical characteristics 4.5.6 hvio i/o high voltage (3.0 v) ac parameters table 31 shows the ac parameters for hvio i/o high voltage (3.0 v). output pad slew rate (high drive) 1 tr, tf 15 pf 35 pf 0.54/0.50 0.29/0.28 v/ns output pad slew rate (medium drive) tr, tf 15 pf 35 pf 0.40/0.38 0.20/0.19 v/ns output pad slew rate (low drive) tr, tf 15 pf 35 pf 0.22/0.21 0.10/0.10 v/ns output pad di/dt (high drive) tdit 34 ma/ns output pad di/dt (medium drive) tdit 22 ma/ns output pad di/dt (low drive) tdit 11 ma/ns input transition times 2 trm 25 ns 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. table 31. hvio i/o high voltage (3.0 v) ac parameters parameter symbol test condition min typ max unit output pad transition times (high drive) tpr 15 pf 35 pf 2.16/1.79 3.75/3.28 ns output pad transition times (medium drive) tpr 15 pf 35 pf 2.81/2.40 5.06/4.58 ns output pad transition times (low drive) tpr 15 pf 35 pf 4.69/4.15 8.91/8.51 ns output pad slew rate (high drive) 1 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. tps 15 pf 35 pf 0.75/0.90 0.43/0.49 v/ns output pad slew rate (medium drive) tps 15 pf 35 pf 0.57/0.67 0.32/0.35 v/ns output pad slew rate (low drive) tps 15 pf 35 pf 0.34/0.39 0.18/0.19 v/ns output pad di/dt (high drive) tdit ? ? ? 55 ma/ns output pad di/dt (medium drive) tdit ? ? ? 36 ma/ns output pad di/dt (low drive) tdit ? ? ? 16 ma/ns input transition times 2 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. trm ? ? ? 25 ns table 30. hvio i/o low voltage (1.8 v) ac parameters (continued) parameter symbol test condition min typ max unit
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 45 4.5.7 ddr2 i/o ac parameters table 32 shows the ac parameters for ddr2 i/o. table 32. ddr2 i/o ac parameters parameter symbol min max unit ac input logic high vih(ac) vref+0.25 - v ac input logic low vil(ac) - vref-0.25 ac differential input voltage 1 1 vid(ac) specifies the input differential voltage |vtr-vcp| required for switching, where vtr is the ?true? input signal and vcp is the ?complementary? input signal. the minimum value is equal to vih(ac)-vil(ac) vid(ac) 0.5 ovdd ac input differential cross point voltage 2 2 the typical value of vix(ac) is expected to be about 0.5*ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. vix(ac) 0.5*ovdd -0.175 0.5*ovdd + 0.175 ac output differential cross point voltage 3 3 the typical value of vox(ac) is expected to be about 0.5*ovdd and vox(ac) is expected to track variation in ovdd. vox(ac) indicates the voltage at which differential output signal must cross. vox(ac) 0.5*ovdd -0.125 0.5*ovdd+ 0.125 output propagation delay high to low t pohld 3.5 ns output propagation delay low to high t polhd 3.5 input propagation delay high to low t pihld 1.5 input propagation delay low to high t pilhd 1.5 single output slew rate tsr 0.4 2 v/ns
i.mx50 applications processors for consumer products, rev. 2 46 freescale semiconductor electrical characteristics 4.5.8 lpddr1 i/o ac parameters table 33 shows the ac parameters for lpddr1 i/o. 4.5.9 lpddr2 i/o ac parameters table 34 shows the ac parameters for lpddr2 i/o. table 33. lpddr1 i/o ac parameters parameter symbol min max unit ac input logic high vihd(ac) 0.8*ovdd ovdd+0.3 v ac input logic low vild(ac) -0.3 0.2*ovdd ac input differential voltage 1 1 vid(ac) specifies the input differential voltage |vtr-vcp| required for switching, where vtr is the ?true? input signal and vcp is the ?complementary? input signal. the minimum value is equal to vih(ac)-vil(ac) vid(ac) 0.6*ovdd ovdd+0.6 ac input differential crosspoint voltage 2 2 the typical value of vix(ac) is expected to be about 0.5*ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. vix(ac) 0.4*ovdd 0.6*ovdd output propagation delay high to low t pohld 2.5 ns output propagation delay low to high t polhd 2.5 input propagation delay high to low t pihld 1.5 input propagation delay low to high t pilhd 1.5 single output slew rate tsr 0.3 2.5 v/ns table 34. lpddr2 i/o ac parameters parameter symbol min max unit ac input logic high vih(ac) vref+0.22 ovdd v ac input logic low vil(ac) ovss vref-0.22 ac differential input high voltage 1 vidh(ac) 0.44 - ac differential input low voltage vidhl(ac) - 0.44 ac input differential cross point voltage (relative to ovdd / 2) 2 vix(ac) -0.12 0.12 over/undershoot peak vpeak 0.35 ns over/undershoot area (above ovdd or below ovss) varea 0.6 (at 266 mhz) v-ns output propagation delay high to low t pohld 3.5 ns output propagation delay low to high t polhd 3.5 input propagation delay high to low t pihld 1.5 input propagation delay low to high t pilhd 1.5
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 47 4.6 system modules timing this section contains the timing and electrical pa rameters for the modules in the i.mx50 processor. 4.6.1 reset timings parameters figure 6 shows the reset timing and table 35 lists the timing parameters. figure 6. reset timing diagram 4.6.2 wdog reset timing parameters figure 7 shows the wdog reset timing and table 36 lists the timing parameters. figure 7. wdog_rst_b timing diagram single output slew rate (driver impedance =40 +/-30%) tsr 1.5 3.5 v/ns single output slew rate (driver impedance =60 +/-30% tsr 1 2.5 v/ns 1 vid(ac) specifies the input differential voltage |vtr-vcp| required for switching, where vtr is the ?true? input signal and vcp is the ?complementary? input signal. the minimum value is equal to vih(ac)-vil(ac). 2 the typical value of vix(ac) is expected to be about 0.5*ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. table 35. reset timing parameters id parameter min max unit cc1 duration of reset_in_b assertion to be qualified as valid (input slope = 5ns) 50 ? ns table 34. lpddr2 i/o ac parameters (continued) parameter symbol min max unit reset_in_b cc1 (input) wdog_rst_b cc5 (input)
i.mx50 applications processors for consumer products, rev. 2 48 freescale semiconductor electrical characteristics note ckil is approximately 32 khz. t ckil is one period or approximately 30 s. 4.6.3 clock amplifier parameters (ckih) the input to clock amplifier (camp) is internally ac- coupled allowing direct interface to a square wave or sinusoidal frequency source. no external series capacitors are required. table 37 shows the electrical parameters of camp. 4.6.4 dpll electrical parameters table 38 shows the electrical parameters of digital phase-locked loop (dpll). table 36. wdog_rst_b timing parameters id parameter min max unit cc5 duration of wdog_rst_b assertion 1 ? t ckil table 37. camp electrical parameters (ckih) parameter min typ max unit input frequency 8.0 ? 40.0 mhz vil (for square wave input) 0 ? 0.3 v vih (for square wave input) (vcc 1 ?0.25) 1 vcc is the supply voltage of camp. ?3 v sinusoidal input amplitude 0.4 2 2 this value of the sinusoidal input is determined during characterization. ?vddvp-p output duty cycle 45 50 55 % table 38. dpll electrical parameters parameter test conditions/remarks min typ max unit reference clock frequency range 1 ? 10 ? 100 mhz reference clock frequency range after pre-divider ?10?40mhz output clock frequency range (dpdck_2) ? 300 ? 1025 mhz pre-division factor 2 ?1?16? multiplication factor integer part ? 5 ? 15 ? multiplication factor numerator 3 should be less than denominator ?67108862 ? 67108862 ? multiplication factor denominator 2 ? 1 ? 67108863 ? output duty cycle ? 48.5 50 51.5 %
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 49 4.6.5 general purpose media interface (gpmi) parameters the i.mx50 gpmi controller is a flexible interface nand flash controller with 8-bit data width, up to 200 mb/s i/o speed and individual chip select. it supports asynchronous timing mode, source s ynchronous timing mode and samsung toggle timing mode separately described in the following paragraphs. 4.6.5.1 asynchronous mode ac timing (onfi 1.0 compatible) asynchronous mode ac timings are provided as multipli cations of the clock cycle and fixed delay. the maximum i/o speed of gpmi in asynchronous mode is about 50 mb/s. figure 8 , figure 9 , figure 10 and figure 11 depict the relative timing between gpmi si gnals at the module level for different frequency lock time 4 (fol mode or non-integer mf) ???398 t dpdref phase lock time ? ? ? 100 s frequency jitter 5 (peak value) ? ? 0.02 0.04 t dck phase jitter (peak value) fpl mode, integer and fractional mf ? 2.0 3.5 ns power dissipation f dck = 300 mhz @ avdd = 1.8 v, dvdd = 1.2 v f dck = 650 mhz @ avdd = 1.8 v, dvdd = 1.2 v ? ? 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) mw 1 device input range cannot exceed the electrical specifications of the camp, see ta ble 3 7 . 2 the values specified here are internal to dpll. inside the dpll, a 1 is added to the value specified by the user. therefore, th e user has to enter a value 1 less than the desired value at the inputs of dpll for pdf and mfd. 3 the maximum total multiplication factor (mfi + mfn/mfd) allowed is 15. therefore, if the mfi value is 15, mfn value must be zero. 4 t dpdref is the time period of the reference clock after predivider. according to the specification, the maximum lock time in fol mode is 398 cycles of divided reference clock when dpll starts after full reset. 5 t dck is the time period of the output clock, dpdck_2. table 38. dpll electrical parameters (continued) parameter test conditions/remarks min typ max unit
i.mx50 applications processors for consumer products, rev. 2 50 freescale semiconductor electrical characteristics operations under asynchronous mode. table 39 describes the timing parameters (nf1?nf17) that are shown in the figures. figure 8. command latch cycle timing diagram figure 9. address latch cycle timing diagram cle cen we ale io[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nf6 nf7 cle cen we ale io[7:0] address nf9 nf8 nf1 nf5 nf3 nf4 nf6 nf11 nf10 nf7
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 51 figure 10. write data latch cycle timing diagram figure 11. read data latch cycle timing diagram table 39. asynchronous mode timing parameters 1 id parameter symbol timing t 2 = gpmi clock cycle 3 example timing for gpmi clock 100 mhz t = 10ns unit min. max. min. max. nf1 cle setup time tcls (as+1)*t ? 10 ? ns nf2 cle hold time tclh (dh+1)*t ? 20 ? ns nf3 cen setup time tcs (as+1)*t ? 10 ? ns nf4 ce hold time tch (dh+1)*t ? 20 ? ns cle cen we ale io[7:0] data to nf nf9 nf8 nf1 nf5 nf3 nf6 nf11 nf10 nf7 cle cen re rb io[7:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16
i.mx50 applications processors for consumer products, rev. 2 52 freescale semiconductor electrical characteristics nf5 we pulse width twp ds*t 10 ns nf6 ale setup time tals (as+1)*t ? 10 ? ns nf7 ale hold time talh (dh+1)*t ? 20 ? ns nf8 data setup time tds ds*t ? 10 ? ns nf9 data hold time tdh dh*t ? 10 ? ns nf10 write cycle time twc (ds+dh)*t 20 ns nf11 we hold time twh dh*t 10 ns nf12 ready to re low trr (as+1)*t ? 10 ? ns nf13 re pulse width trp ds*t ? 10 ? ns nf14 read cycle time trc (ds+dh)*t ? 20 ? ns nf15 re high hold time treh dh*t 10 ? ns nf16 data setup on read tdsr n/a 10 ? ns nf17 data hold on read tdhr n/a 10 ? ns 1 gpmi?s async mode output timing could be controlled by module?s internal register, say hw_gpmi_timing0_address_setup, hw_gpmi_timing0_ data_setup, and hw_gpmi_timing0_data_hold. this ac timing depends on these registers? setting. in the above table, we use as/ds/dh representing these settings each. 2 t represents for the gpmi clock period. 3 as minimum value could be 0, while ds/dh minimum value is 1. table 39. asynchronous mode timing parameters 1 (continued) id parameter symbol timing t 2 = gpmi clock cycle 3 example timing for gpmi clock 100 mhz t = 10ns unit min. max. min. max.
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 53 4.6.5.2 source synchronous mode ac timing (onfi 2.x compatible) the following diagrams show the write and read timing of source synchronous mode. figure 12. source synchronous mode command and address timing diagram ce_n cle ale clk dqs w/r# dq[7:0] cmd nf20 nf21 nf22 nf23 nf18 nf19 dqs output enable dq[7:0] output enable nf24 add add nf20 nf21
i.mx50 applications processors for consumer products, rev. 2 54 freescale semiconductor electrical characteristics figure 13. source synchronous mode data write timing diagram ce_n cle ale clk dqs w/r# dq[7:0] nf22 nf23 nf18 nf19 dqs output enable dq[7:0] output enable nf24 nf27 nf27 nf27 nf25 nf25 nf26
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 55 figure 14. source synchronous mode data read timing diagram table 40. source synchronous mode timing parameters 1 id parameter symbol timing t = gpmi clock cycle unit min. max. nf18 ce# access time t ce ce_delay*t ck ?ns nf19 ce# hold time t ch 0.5 *t ck ?ns nf20 command/address dq setup time t cas 0.5*t ck ?ns nf21 command/address dq hold time t cah 0.5*t ck ?ns nf22 clock period t ck 5?ns nf23 preamble delay t pre pre_delay*t ck ?ns ce_n cle ale clk dqs w/r# dq[7:0] nf22 nf23 nf18 nf19 dqs output enable dq[7:0] output enable nf24 nf25 nf25 nf25 nf26
i.mx50 applications processors for consumer products, rev. 2 56 freescale semiconductor electrical characteristics 4.6.5.3 samsung toggle mode ac timing 4.6.5.3.1 command and address timing note samsung toggle mode command and addr ess timing is the same as onfi 1.0 compatible async mode ac timing. please refer to the above chapter for details. nf24 postamble delay t post post_delay*t ck ?ns nf25 cle and ale setup time t cals 0.5*t ck ?ns nf26 cle and ale hold time t calh 0.5*t ck ?ns nf27 data input to first dqs latching transition t dqss t ck ?ns 1 gpmi?s sync mode output timing could be controlled by module?s internal register, say hw_gpmi_timing2_ce_delay, hw_gpmi_timing_preamble_delay, and hw_gpmi_timing2_post_delay. this ac timing depends on these registers? setting. in the above table, we use ce_delay/pre_delay/post_delay representing these settings each. table 40. source synchronous mode timing parameters 1 (continued) id parameter symbol timing t = gpmi clock cycle unit min. max.
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 57 4.6.5.3.2 read and write timing figure 15. samsung toggle mode data write timing ce_n cle ale we_n dqs re_n dq[7:0] nf23 0.5 tck nf22 nf24 0.5 tck 0 0 0 1 1 dev_clk
i.mx50 applications processors for consumer products, rev. 2 58 freescale semiconductor electrical characteristics figure 16. samsung toggle mode data read timing table 41. samsung toggle mode timing parameters 1 id parameter symbol timing t = gpmi clock cycle unit min. max. nf18 ce# access time t ce ce_delay*t ck ?ns nf19 ce# hold time t ch 0.5 *t ck ?ns nf20 command/address dq setup time t cas 0.5*t ck ?ns nf21 command/address dq hold time t cah 0.5*t ck ?ns nf22 clock period t ck 7.5 ? ns ce_n cle ale we_n dqs re_n dq[7:0] nf23 nf24 0 0 1 1 tck 1 tck 1 tck nf18 dev_clk 1 tck 1 tck
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 59 4.7 external interface module (eim) the following sections provide information on the eim. 4.7.1 general eim timing figure 17 , figure 18 , and table 42 specify the timings related to the eim module. all eim output control signals may be asserted and de-asserted by an intern al clock synchronized to the eim_bclk rising edge according to corresponding assertion/negation control fields. , figure 17. eim outputs timing diagram nf23 preamble delay t pre (pre_delay+1)*t ck ?ns nf24 postamble delay t post post_delay*t ck ?ns nf25 cle and ale setup time t cals 0.5*t ck ?ns nf26 cle and ale hold time t calh 0.5*t ck ?ns 1 gpmi?s sync mode output timing could be controlled by module?s internal register, say hw_gpmi_timing2_ce_delay, hw_gpmi_timing_preamble_delay, hw_gpmi_timing2_post_delay. this ac timing depends on these registers? setting. in the above table, we use ce_delay/pre_delay/post_delay representing these settings each. table 41. samsung toggle mode timing parameters 1 (continued) id parameter symbol timing t = gpmi clock cycle unit min. max. we4 eim_addr eim_csx eim_rw eim_oe eim_bclk eim_ebx eim_lba eim_data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1
i.mx50 applications processors for consumer products, rev. 2 60 freescale semiconductor electrical characteristics figure 18. eim inputs timing diagram eim_data eim_wait eim_bclk we19 we18 we21 we20
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 61 table 42. eim bus timing parameters 1 1 t is axi_clk cycle time. the maximum allowed axi_clk frequency is 133 mhz, whereas the maximum allowed eim_bclk frequency is 66.5 mhz. as a result, if bcd = 0, axi_clk must be 66.5 mhz. if bcd = 1, then 133 mhz is allowed for axi_clk, resulting in a eim_bclk of 66.5 mhz. when the clock branch to eim is decreased to 66.5 mhz, other buses are impacted which are clocked from this source. see the ccm chapter of the mcimx50 applications processor reference manual (mcimx50rm) for a detailed clock tree description. id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max we1 eim_bclk cycle time 2 t?2t?3t?4t? we2 eim_bclk low level width 0.4t ? 0.8t ? 1.2t ? 1.6t ? we3 eim_bclk high level width 0.4t ? 0.8t ? 1.2t ? 1.6t ? we4 clock rise to address valid 3 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we5 clock rise to address invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we6 clock rise to eim_csx valid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we7 clock rise to eim_csx invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we8 clock rise to eim_rw valid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we9 clock rise to eim_rw invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we10 clock rise to eim_oe valid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we11 clock rise to eim_oe invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we12 clock rise to eim_ebx valid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we13 clock rise to eim_ebx invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we14 clock rise to eim_lba valid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we15 clock rise to eim_lba invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 3t ? 1.25 3t + 1.75 we16 clock rise to output data valid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 2t ? 1.25 2t + 1.75 we17 clock rise to output data invalid 0.5t ? 1.25 0.5t + 1.75 t ? 1.25 t + 1.75 2t ? 1.25 2t + 1.75 2t ? 1.25 2t + 1.75 we18 input data setup time to clock rise 2 ?2?2?2? we19 input data hold time from clock rise 2.5 ? 2.5 ? 2.5 ? 2.5 ? we20 eim_wait setup time to clock rise 2 ?2?2?2? we21 eim_wait hold time from clock rise 2.5 ? 2.5 ? 2.5 ? 2.5 ?
i.mx50 applications processors for consumer products, rev. 2 62 freescale semiconductor electrical characteristics 4.7.2 examples of eim accesses figure 19 , figure 20 , figure 21 , figure 22 , figure 23 , and figure 24 give a few examples of basic eim accesses to external memory devices with the timing pa rameters mentioned previously for specific control parameters settings. figure 19. synchronous memory read access, wsc=1 2 eim_bclk parameters are being measured from the 50% point that is, high is defined as 50% of signal value and low is defined as 50% as signal value. 3 for signal measurements high is defined as 80% of signal value and low is defined as 20% of signal value. last valid address address v1 d(v1) eim_bclk eim_addr eim_data eim_rw eim_lba eim_oe eim_ebx eim_csx next address we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we19
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 63 figure 20. synchronous memory, write access, wsc=1, wbea=1, wben=1, and wadvn=0 figure 21. synchronous 16-bit memory, two non-sequential 32-bit read accesses, wsc=2, srd=1, bcd=0 last valid address address v1 d(v1) eim_bclk eim_addr eim_data eim_rw eim_lba eim_oe eim_ebx eim_csx next address we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17 last valid addr address v1 address v2 d(v1) d(v1+1) d(v2) d(v2+1) eim_bclk eim_addr eim_wait eim_data halfword halfword eim_csx eim_rw eim_lba eim_oe eim_ebx halfword halfword we4 we5 we7 we10 we11 we12 we13 we14 we15 we18 we19 we20 we21 we6 we15 we14
i.mx50 applications processors for consumer products, rev. 2 64 freescale semiconductor electrical characteristics figure 22. synchronous memory, burst write, bcs=1, wsc=4, srd=1, and bcd=0 figure 23. muxed address/data (a/d) mode, synchronous write access, wsc=6, adva=1, advn=1, and adh=1 note in 32-bit muxed address/data (a/d) mode, the 16 msbs are driven on the data bus. last valid addr eim_bclk eim_addr eim_data eim_csx eim_rw eim_lba eim_oe eim_ebx eim_wait address v1 d(v1) d(v2) d(v4) d(v3) we12 we4 we5 we6 we7 we8 we9 we13 we14 we16 we16 we17 we17 we20 we21 we15 last eim_bclk eim_addr/ eim_rw eim_lba eim_oe eim_ebx eim_csx address v1 write data valid addr eim_data we4 we16 we6 we7 we9 we8 we10 we11 we14 we15 we17 we5
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 65 figure 24. 16-bit muxed a/d mode, synchronous read access, wsc=7, radvn=1, adh=1, oea=2 figure 25 , figure 26 , figure 27 , and table 43 help to determine timing parameters relative to the chip select (cs) state for asynchronous and dtack eim accesses with corresponding eim bit fields and the timing parameters mentioned above. figure 25. asynchronous memory read access last eim_bclk eim_addr/ eim_rw eim_lba eim_oe eim_ebx eim_csx address v1 data valid addr eim_data we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we19 we4 last valid address address v1 d(v1) eim_addr eim_data eim_rw eim_lba eim_oe eim_ebx eim_csx next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44
i.mx50 applications processors for consumer products, rev. 2 66 freescale semiconductor electrical characteristics figure 26. asynchronous memory write access figure 27. dtack read access table 43. eim asynchronous timing parameters table relative chip select id parameter determination by synchronous measured parameters 1 min max unit we31 eim_csx valid to address valid we4 ? we6 ? csa 2 ? 3 ? csa ns we32 address invalid to eim_csx invalid we7 ? we5 ? csn 3 ?3 ? csnns we33 eim_csx valid to eim_rw valid we8 ? we6 + (wea ? csa) ? 3 + (wea ? csa) ns last valid address address v1 d(v1) eim_addr eim_data eim_rw eim_lba eim_oe eim_ebx eim_csx next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 last valid address address v1 d(v1) eim_addr eim_data eim_rw eim_lba eim_oe eim_ebx eim_csx next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 eim_dtack we47 we48
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 67 4.8 dram timing parameters this section includes descriptions of the electrica l specifications of dram mc module which interfaces external ddr2, lpddr1, and lpddr2 memory devices. we34 eim_rw invalid to eim_csx invalid we7 ? we9 + (wen ? csn) ? 3 ? (wen_csn) ns we35 eim_csx valid to eim_oe valid we10 ? we6 + (oea ? csa) ? 3 + (oea ? csa) ns we36 eim_oe invalid to eim_csx invalid we7 ? we11 + (oen ? csn) ? 3 ? (oen ? csn) ns we37 eim_csx valid to eim_ebx valid (read access) we12 ? we6 + (rbea ? csa) ? 3 + (rbea 4 ? csa) ns we38 eim_ebx invalid to eim_csx invalid (read access) we7 ? we13 + (rben ? csn) ? 3 ? (rben 5 ? csn) ns we39 eim_csx valid to eim_lba valid we14 ? we6 + (adv ? csa) ? 3 + (adva ? csa) ns we40 eim_lba invalid to eim_csx invalid (advl is asserted) we7 ? we15 ? csn ? 3 ? csn ns we41 eim_csx valid to output data valid we16 ? we6 ? wcsa ? 3 ? wcsa ns we42 output data invalid to eim_csx invalid we17 ? we7 ? csn ? 3 ? csn ns we43 input data valid to eim_csx invalid maxco + maxdi maxco 6 + maxdi 7 ?ns we44 eim_csx invalid to input data invalid 0 0 ? ns we45 eim_csx valid to eim_ebx valid (write access) we12 ? we6 + (wbea ? csa) ? 3 + (wbea ? csa) ns we46 eim_ebx invalid to eim_csx invalid (write access) we7 ? we13 + (wben ? csn) ? ?3 + (wben ? csn) ns we47 eim_dtack valid to eim_csx invalid maxco + maxdti maxco 6 +ma xdti 8 ?ns we48 eim_csx invalid to eim_dtack invalid 00?ns 1 parameters we4?we21 value, see in the ta b l e 4 3 . 2 eim_csx assertion. this bit field determines when eim_csx signal is asserted during read/write cycles. 3 eim_csx negation. this bit field determines when eim_csx signal is negated during read/write cycles. 4 eim_ebx assertion. this bit field determines when eim_ebx signal is asserted during read cycles. 5 eim_ebx negation. this bit field determines when eim_ebx signal is negated during read cycles. 6 output maximum delay from internal driving the ffs to chip outputs. the maximum delay between all memory controls (eim_addr, eim_csx, eim_oe, eim_rw, eim_ebx, and eim_lba). 7 maximum delay from chip input data to internal ffs. the maximum delay between all data input pins. 8 dtack maximum delay from chip input data to internal ff. table 43. eim asynchronous timing parameters table relative chip select (continued) id parameter determination by synchronous measured parameters 1 min max unit
i.mx50 applications processors for consumer products, rev. 2 68 freescale semiconductor electrical characteristics 4.8.1 dram command & address output timing?ddr2 and lpddr1 the following diagrams and tables specify the timings related to the address and command pins, which interfaces ddr2 and lpddr1 memory devices. table 44. emi command/address ac timing id description symbol min max unit ddr1 ck cycle time tck 3.75 ? ns ddr2 ck high level width tch 0.48 tck 0.52 tck ns ddr3 ck low level width tcl 0.48 tck 0.52 tck ns ddr4 address and control output setup time tis 0.5 tck - 0.3 ?ns ddr5 address and control output hold time tih 0.5 tck - 0.3 ?ns figure 28. dram command/address output timing?ddr2 and lpddr1 dram_sdclk dram_sdclk_b dram_cs0 dram_ras dram_cas dram_sdwe bank row bank column dram_addr ddr1 ddr2 ddr3 ddr4 ddr5 ddr4 ddr5 ddr4 ddr5
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 69 4.8.2 dram command and address output timing?lpddr2 the following diagrams and tables specify the timings related to the address and command pins, which interface lpddr2 memory devices. table 45. emi command/address ac timing id description symbol min max unit ddr1 ck cycle time tck 3.75 ? ns ddr2 ck high level width tch 0.48 tck 0.52 tck ns ddr3 ck low level width tcl 0.48 tck 0.52 tck ns ddr4 control output setup time tis 0.5 tck - 0.3 ?ns ddr5 control output hold time tih 0.5 tck - 0.3 ?ns ddr6 ck >= 200 mhz address output setup time tis 0.5 tck - 1.3 ?ns ddr7 ck >= 200 mhz address output hold time tih 0.5 tck - 1.3 ?ns ddr6 ck < 200 mhz address output setup time tis 1 ? ns ddr7 ck < 200 mhz address output hold time tih 1 ? ns figure 29. dram command/address output timing?lpddr2 dram_sdclk dram_sdclk_b dram_cs0 dram_a[9:0] ddr1 ddr2 ddr3 ddr4 ddr5 rise fall ddr6 ddr7
i.mx50 applications processors for consumer products, rev. 2 70 freescale semiconductor electrical characteristics note ddr6 and ddr7 can be adjusted by the parameter -dll_wr_delay-; the ideal case is that sdclk is center aligned to the dram_a[9:0] data valid window; for this table, hw_dram_phy23[14:8] (dll_wr_delay) = 0x10; 4.8.3 dram data output timing the dram data output timing is defined for all ddr types: ddr2, lpddr1, and lpddr2. table 46. ddr output ac timing id description symbol min max unit ddr10 positive dqs latching edge to associated ck edge tdqss -0.3 0.3 ns ddr11 dqs falling edge from ck rising edge?hold time tdsh 0.5 tck - 0.3 0.5 tck + 0.3 ns ddr12 dqs falling edge to ck rising edge?setup time tdss 0.5 tck - 0.3 0.5 tck + 0.3 ns ddr13 dqs output high pulse width tdqsh 0.48 tck 0.52 tck ns ddr14 dqs output low pulse width tdqsl 0.48 tck 0.52 tck ns ddr15 ck >= 200 mhz dq & dqm output setup time relative to dqs tds 0.5 tck - 1.3 ?ns figure 30. dram data output timing dram_sdclk dram_sdclk_b dram_sdqs ddr13 ddr14 d0 ddr10 d1 d2 d3 dram_d & dram_dqm ddr11 ddr12 ddr15 ddr16 dram_sdqs_b
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 71 note the ddr15,16 could be adjusted by the parameter ?dll_wr_delay?; the ideal case is that sdqs is center aligned to the dram_d data valid window; for this table, hw_dram_phy15[14:8] (dll_wr_delay) = 0x10; 4.8.4 dram data input timing dram data input timing is defined for a ll ddr types: ddr2, lpddr1, and lpddr2. ddr16 ck >= 200 mhz dq & dqm output hold time relative to dqs tdh 0.5 tck - 1.3 ?ns ddr15 ck < 200 mhz dq & dqm output setup time relative to dqs tds 1 ? ns ddr16 ck < 200 mhz dq & dqm output hold time relative to dqs tdh 1 ? ns table 47. ddr2 input ac timing id description symbol min max unit ddr20 positive dqs latching edge to associated ck edge tdqsck -0.5 tck ? ns table 46. ddr output ac timing id description symbol min max unit figure 31. dram data input timing dram_sdclk dram_sdclk_b dram_sdqs ddr21 ddr22 d0 ddr20 d1 d2 d3 dram_d dram_sdqs_b
i.mx50 applications processors for consumer products, rev. 2 72 freescale semiconductor electrical characteristics note the timing parameter ddr20(tdqsck) is not strictly required by this dram mc design. 4.9 external peripheral interfaces the following sections provide information on external peripheral interfaces. 4.9.1 audmux timing parameters the audmux provides programmable interconnect logi c for voice, audio and data routing between internal serial interfaces (ssis) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is hence governed by the ssi module. 4.9.2 cspi and ecspi timing parameters this section describes the timing parameters of th e cspi and ecspi modules. the cspi and ecspi have separate timing parameters for master and slave modes. the nomenclature used with the cspi/ecspi modules and the respective routing of these signals is shown in table 48 . ddr21 dqs to dq input skew tdqsq ? 0.65 ns ddr22 dqs to dq input hold time tqh 0.45 tck -0.85 ?ns table 48. cspi nomenclature and routing module i/o access ecspi1 gpio, kpp, disp0_dat, csi0_dat, and eim_d through iomux ecspi2 disp0_dat, csi0_dat, and eim through iomux cspi disp0_dat, eim_a/d, sd1, and sd2 through iomux table 47. ddr2 input ac timing id description symbol min max unit
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 73 4.9.2.1 cspi master mode timing figure 32 depicts the timing of cspi in master mode and table 49 lists the cspi master mode timing characteristics. figure 32. cspi master mode timing diagram table 49. cspi master mode timing parameters id parameter symbol min max unit cs1 cspix_clk cycle time t clk 60 ? ns cs2 cspix_clk high or low time t sw 6?ns cs3 cspix_clk rise or fall t rise/fall ??ns cs4 cspix_cs_x pulse width t cslh 15 ? ns cs5 cspix_cs_x lead time (cs setup time) t scs 5?ns cs6 cspix_cs_x lag time (cs hold time) t hcs 5?ns cs7 cspix_do setup time t smosi 5?ns cs8 cspix_do hold time t hmosi 5?ns cs9 cspix_di setup time t smiso 5?ns cs10 cspix_di hold time t hmiso 5?ns cs11 cspix_dryn setup time t sdry 5?ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 cspix_clk cspix_cs_x cspix_do cspix_di cspix_dryn1 cs11 cs3 cs3
i.mx50 applications processors for consumer products, rev. 2 74 freescale semiconductor electrical characteristics 4.9.2.2 cspi slave mode timing figure 33 depicts the timing of cspi in slave mode. table 50 lists the cspi slave mode timing characteristics. figure 33. cspi slave mode timing diagram table 50. cspi slave mode timing parameters id parameter symbol min max unit cs1 cspix_clk cycle time t clk 60 ? ns cs2 cspix_clk high or low time t sw 15 ? ns cs3 cspix_clk rise or fall t rise/fall ??ns cs4 cspix_cs_x pulse width t cslh 30 ? ns cs5 cspix_cs_x lead time (cs setup time) t scs 5?ns cs6 cspix_cs_x lag time (cs hold time) t hcs 5?ns cs7 cspix_do setup time t smosi 5?ns cs8 cspix_do hold time t hmosi 5?ns cs9 cspix_di setup time t smiso 5?ns cs10 cspix_di hold time t hmiso 5?ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 cspix_clk cspix_cs_x cspix_di cspix_do cs3 cs3
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 75 4.9.2.3 ecspi master mode timing figure 34 depicts the timing of ecspi in master mode and table 51 lists the ecspi master mode timing characteristics. figure 34. ecspi master mode timing diagram table 51. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_clk cycle time?read ecspix_clk cycle time?write t clk 60 15 ?ns cs2 ecspix_clk high or low time t sw 6?ns cs3 ecspix_clk rise or fall t rise/fall ??ns cs4 ecspix_cs_x pulse width t cslh 15 ? ns cs5 ecspix_cs_x lead time (cs setup time) t scs 5?ns cs6 ecspix_cs_x lag time (cs hold time) t hcs 5?ns cs7 ecspix_do setup time t smosi 5?ns cs8 ecspix_do hold time t hmosi 5?ns cs9 ecspix_di setup time t smiso 5?ns cs10 ecspix_di hold time t hmiso 5?ns cs11 ecspix_dryn setup time t sdry 5?ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 ecspix_clk ecspix_cs_x ecspix_do ecspix_di ecspix_dryn1 cs11 cs3 cs3
i.mx50 applications processors for consumer products, rev. 2 76 freescale semiconductor electrical characteristics 4.9.2.4 ecspi slave mode timing figure 35 depicts the timing of ecspi in slave mode and table 52 lists the ecspi slave mode timing characteristics. figure 35. ecspi slave mode timing diagram table 52. ecspi slave mode timing parameters id parameter symbol min max unit cs1 ecspix_clk cycle time?read ecspix_clk cycle time?write t clk 60 15 ?ns cs2 ecspix_clk high or low time t sw 6?ns cs3 ecspix_clk rise or fall t rise/fall ??ns cs4 ecspix_cs_x pulse width t cslh 15 ? ns cs5 ecspix_cs_x lead time (cs setup time) t scs 5?ns cs6 ecspix_cs_x lag time (cs hold time) t hcs 5?ns cs7 ecspix_do setup time t smosi 5?ns cs8 ecspix_do hold time t hmosi 5?ns cs9 ecspix_di setup time t smiso 5?ns cs10 ecspix_di hold time t hmiso 5?ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 ecspix_clk ecspix_cs_x ecspix_di ecspix_do cs3 cs3
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 77 4.9.3 enhanced secured digital host controller (esdhcv2/v3) and usdhc ac timing this section describes the electrical informa tion of the esdhcv2/v3 and the usdhc, which includes sd/emmc4.3 (single data rate) timing and emmc4.4 (dual date rate) timing. 4.9.3.1 sd/emmc4.3 (single data rate) esdhcv3 and usdhc ac timing figure 36 depicts the timing of sd/emmc4.3, and table 53 lists the sd/emmc4.3 timing characteristics. figure 36. sd/emmc4.3 timing table 53. sd/emmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0400khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns sd1 sd3 sd5 sd4 sd7 cmd output from esdhcv2 to card dat1 ...... dat7 dat0 cmd input from card to esdhcv2 dat1 ...... dat7 dat0 sck sd2 sd8 sd6
i.mx50 applications processors for consumer products, rev. 2 78 freescale semiconductor electrical characteristics 4.9.3.2 emmc4.4 (dual data rate) esdhcv3 and usdhc ac timing figure 37 depicts the timing of emmc4.4, and table 54 lists the emmc4.4 timing characteristics. be aware that only dat0-7 is sampled on both edges of clock (not applicable to cmd). figure 37. emmc4.4 timing esdhc output/card inputs cmd, dat (reference to clk) sd6 esdhc output delay t od ?22ns esdhc input/card outputs cmd, dat (reference to clk) sd7 esdhc input setup time t isu 2.5 ? ns sd8 esdhc input hold time 4 t ih 2.5 ? ns 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 2 in normal (full) speed mode for sd/sdio card, clock frequency can be any value between 0?25 mhz. in high-speed mode, clock frequency can be any value between 0?50 mhz. 3 in normal (full) speed mode for mmc card, clock frequency can be any value between 0?20 mhz. in high-speed mode, clock frequency can be any value between 0?52 mhz. 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. table 54. emmc4.4 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (mmc full speed/high speed) f pp 052 mhz esdhc output/card inputs cmd, dat (reference to clk) table 53. sd/emmc4.3 interface timing specification (continued) id parameter symbols min max unit sd1 sd2 sd3 output from esdhcv3 to card dat1 ...... dat7 dat0 input from card to esdhcv3 dat1 ...... dat7 dat0 sck sd4 sd2 ...... ......
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 79 4.9.4 fec ac timing parameters this section describes the ac timing specifications of the fec. the i.mx50 fec supports 10/100 mbps rmii with mii serial management interface. the rmii and serial management signals are compatible with transceivers operating at a voltage of 3.3 v. 4.9.4.1 rmii async inputs signal timing (fec_col) table 55 lists rmii asynchronous inputs signal timing information. figure 38 shows mii asynchronous input timings listed in table 55 . . figure 38. mii async inputs timing diagram 4.9.4.2 rmii serial management channel timing (fec_mdio and fec_mdc) table 56 lists rmii serial mana gement channel timings. figure 39 shows rmii serial management channel timings listed in table 56 . the mdc frequency should be equal to or less than 2.5 mhz to be compliant with the ieee 802.3 rmii specification. however, the fec can function correctly with a maximum mdc frequency of 15 mhz. sd2 esdhc output delay t od ?5 5 ns esdhc input/card outputs cmd, dat (reference to clk) sd3 esdhc input setup time t isu 2.5 ? ns sd4 esdhc input hold time t ih 1.5 ? ns table 55. rmii async inputs signal timing num characteristics min max unit m9 fec_col minimum pulse width 1.5 ? fec_tx_clk period table 56. rmii transmit signal timing id characteristics min max unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0 ? ns m11 fec_mdc falling edge to fec_mdio output valid (max propagation delay) ? 5 ns m12 fec_mdio (input) to fec_mdc rising edge setup 18 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns table 54. emmc4.4 interface timing specification (continued) id parameter symbols min max unit fec_col m9
i.mx50 applications processors for consumer products, rev. 2 80 freescale semiconductor electrical characteristics figure 39. rmii serial management channel timing diagram 4.9.4.3 rmii mode timing in rmii mode, fec_tx_clk is used as the ref_clk which is a 50 mhz 50 ppm continuous reference clock. fec_rx_dv is used as the crs _dv in rmii, and other signals under rmii mode include fec_tx_en, fec_txd[1:0], fec_rxd[1:0] and optional fec_rx_er. the rmii mode timings are shown in table 57 and figure 40 . m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period table 57. rmii signal timing no. characteristics min max unit m16 ref_clk(fec_tx_clk) pulse width high 35% 65% ref_clk period m17 ref_clk(fec_tx_clk) pulse width low 35% 65% ref_clk period m18 ref_clk to fec_txd[1:0], fec_tx_en invalid 2 ? ns m19 ref_clk to fec_txd[1:0], fec_tx_en valid ? 16 ns m20 fec_rxd[1:0], crs_dv(fec_rx_dv), fec_rx_er to ref_clk setup 4?ns m21 ref_clk to fec_rxd[1:0], fec_rx_dv, fec_rx_er hold 2 ? ns table 56. rmii transmit signal timing (continued) id characteristics min max unit fec_mdc (output) fec_mdio (output) m14 m15 m10 m11 m12 m13 fec_mdio (input)
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 81 figure 40. rmii mode signal timing diagram 4.9.5 i 2 c module timing parameters this section describes the timing parameters of the i 2 c module. figure 41 depicts the timing of i 2 c module, and table 58 lists the i 2 c module timing characteristics. figure 41. i 2 c bus timing table 58 . i 2 c module timing parameters id parameter standard mode supply voltage = 1.65 v?1.95 v, 2.7 v?3.3 v fast mode supply voltage = 2.7 v?3.3 v unit min max min max ic1 i2clk cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ref_clk (input) fec_tx_en m16 m17 m18 m19 m20 m21 fec_rxd[1:0] fec_txd[1:0] (output) fec_rx_er crs_dv (input) ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2dat i2clk ic1
i.mx50 applications processors for consumer products, rev. 2 82 freescale semiconductor electrical characteristics 4.9.6 one-wire (owire) timing parameters figure 42 depicts the rpp timing, and table 59 lists the rpp timing parameters. figure 42. reset and presence pulses (rpp) timing diagram ic4 data hold time 0 1 3.45 2 0 1 0.9 2 s ic5 high period of i2clk clock 4.0 ? 0.6 ? s ic6 low period of the i2clk clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2dat and i2clk signals ? 1000 20 + 0.1c b 4 300 ns ic11 fall time of both i2dat and i2clk signals ? 300 20 + 0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf 1 a device must internally provide a hold time of at least 300 ns for i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2clk signal. 3 a fast-mode i 2 c-bus device can be used in a standard-mode i2c-bus system, but the requirement of set-up time (id no ic7) of 250 ns must be met. this automatically is the case if the device does not stretch the low period of the i2clk signal. if such a device does stretch the low period of the i2clk signal, it must output the next data bit to the i2dat line max_rise_time (ic9) + data_setup_time (ic7) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the i2clk line is released. 4 c b = total capacitance of one bus line in pf. table 5 8. i 2 c module timing parameters (continued) id parameter standard mode supply voltage = 1.65 v?1.95 v, 2.7 v?3.3 v fast mode supply voltage = 2.7 v?3.3 v unit min max min max one-wire bus one wire device tx ?presence pulse? (batt_line) one-wire tx ?reset pulse? ow1 ow2 ow3 ow4 t r
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 83 figure 43 depicts write 0 sequence timing, and table 60 lists the timing parameters. figure 43. write 0 sequence timing diagram figure 44 depicts write 1 sequence timing, figure 45 depicts the read sequence timing, and table 61 lists the timing parameters. figure 44. write 1 sequence timing diagram table 59. rpp sequence delay comparisons timing parameters id parameters symbol min typ max unit ow1 reset time low t rstl 480 511 ? 1 1 in order not to mask signaling by other devices on the 1-wire bus, t rstl +t r should always be less than 960 s. s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high (includes recovery time) t rsth 480 512 ? s table 60. wr0 sequence timing parameters id parameter symbol min typ max unit ow5 write 0 low time t low0 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s ? recovery time t rec 1??s ow5 ow6 one-wire bus (batt_line) t rec ow7 ow8 one-wire bus (batt_line)
i.mx50 applications processors for consumer products, rev. 2 84 freescale semiconductor electrical characteristics figure 45. read sequence timing diagram 4.9.7 pulse width modulator (pwm) timing parameters this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. figure 46 depicts the timing of the pwm, and table 62 lists the pwm timing parameters. figure 46. pwm timing table 61. wr1 /rd timing parameters id parameter symbol min typ max unit ow7 write 1 low time t low1 1515s ow8 transmission time slot t slot 60 117 120 s ? read data setup t su ??1s ow9 read low time t lowr 1515s ow10 read data valid t rdv ?15?s ow11 release time t release 0?45s t su ow8 ow10 one-wire bus (batt_line) ow9 ow11 system clock 2a 1 pwm output 3b 2b 3a 4b 4a
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 85 4.9.8 secure jtag controller (sjc) timing parameters figure 47 depicts the sjc test clock input timing. figure 48 depicts the sjc boundary scan timing. figure 49 depicts the sjc test access port. figure 50 depicts the trst timing. the signal parameters are listed in table 63 . figure 47. test clock input timing diagram table 62. pwm output timing parameter ref. no. parameter min max unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 0 ipg_clk mhz 2a clock high time 12.29 ? ns 2b clock low time 9.91 ? ns 3a clock fall time ? 0.5 ns 3b clock rise time ? 0.5 ns 4a output delay time ? 9.37 ns 4b output setup time 8.71 ? ns tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3
i.mx50 applications processors for consumer products, rev. 2 86 freescale semiconductor electrical characteristics figure 48. boundary scan (jtag) timing diagram figure 49. test access port timing diagram tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 87 figure 50. trst timing diagram table 63. jtag timing id parameter 1,2 all frequencies unit min max sj0 tck frequency of operation 1/(3?t dc ) 1 1 t dc = target frequency of sjc 0.001 22 mhz sj1 tck cycle time in crystal mode 45 ? ns sj2 tck clock pulse width measured at v m 2 2 v m = mid-point voltage 22.5 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 tck low to output data valid ? 40 ns sj7 tck low to output high impedance ? 40 ns sj8 tms, tdi data set-up time 5 ? ns sj9 tms, tdi data hold time 25 ? ns sj10 tck low to tdo data valid ? 44 ns sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns tck (input) trst (input) sj13 sj12
i.mx50 applications processors for consumer products, rev. 2 88 freescale semiconductor electrical characteristics 4.9.9 ssi timing parameters this section describes the timing parameters of the ssi module. the connectivity of the serial synchronous interfaces are summarized in table 64 . note ? the terms wl and bl used in the timing diagrams and tables refer to word length (wl) and bit length (bl). ? the ssi timing diagrams use gene ric signal names wherein the names used in the mcimx50 applications processor reference manual (mcimx50rm) are channel specific signal names. for example, a channel clock referenced in the iomuxc chapter as aud3_txc appears in the timing diagram as txc. table 64. audmux port allocation port signal nomenclature type and access audmux port 1 ssi 1 internal audmux port 2 ssi 2 internal audmux port 3 aud3 external? aud3 i/o audmux port 4 aud4 external?eim or cspi1 i/o through iomux audmux port 5 aud5 external?eim or sd1 i/o through iomux audmux port 6 aud6 external?eim or disp2 through iomux
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 89 4.9.9.1 ssi transmitter timing with internal clock figure 51 depicts the ssi transmitter internal clock timing and table 65 lists the timing parameters for the ssi transmitter internal clock. . figure 51. ssi transmitter internal clock timing diagram table 65. ssi transmitter timing with internal clock id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6.0 ns ss15 (tx/rx) internal fs fall time ? 6.0 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss19 ss1 ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only txc (output) txfs (wl) (output) txfs (bl) (output) rxd (input) txd (output)
i.mx50 applications processors for consumer products, rev. 2 90 freescale semiconductor electrical characteristics note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in both the tables and figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? tx and rx refer to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6.0 ns synchronous internal clock operation ss42 srxd setup before (tx) ck falling 10.0 ? ns ss43 srxd hold after (tx) ck falling 0.0 ? ns ss52 loading ? 25.0 pf table 65. ssi transmitter timing with internal clock (continued) id parameter min max unit
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 91 4.9.9.2 ssi receiver timing with internal clock figure 52 depicts the ssi receiver internal clock timing and table 66 lists the timing parameters for the receiver timing with internal clock. figure 52. ssi receiver internal clock timing diagram table 66. ssi receiver timing with internal clock id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 10.0 ? ns ss21 srxd hold time after (rx) ck low 0.0 ? ns ss50 ss48 ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 ss3 ss5 txc (output) txfs (bl) (output) txfs (wl) (output) rxd (input) rxc (output)
i.mx50 applications processors for consumer products, rev. 2 92 freescale semiconductor electrical characteristics note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs as shown in both the tables and figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? tx and rx refer to the transmit and receive sections of the ssi. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). oversampling clock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6.0 ? ns ss49 oversampling clock rise time ? 3.0 ns ss50 oversampling clock low period 6.0 ? ns ss51 oversampling clock fall time ? 3.0 ns table 66. ssi receiver timing with internal clock (continued) id parameter min max unit
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 93 4.9.9.3 ssi transmitter timing with external clock figure 53 depicts the ssi transmitter external clock timing and table 67 lists the timing parameters for the transmitter timing with external clock. figure 53. ssi transmitter external clock timing diagram table 67. ssi transmitter timing with external clock id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 (tx) ck high to fs (bl) high ?10.0 15.0 ns ss29 (tx) ck high to fs (bl) low 10.0 ? ns ss31 (tx) ck high to fs (wl) high ?10.0 15.0 ns ss33 (tx) ck high to fs (wl) low 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 15.0 ns ss45 ss33 ss24 ss26 ss25 ss23 note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 txc (input) txfs (bl) (input) txfs (wl) (input) txd (output) rxd (input)
i.mx50 applications processors for consumer products, rev. 2 94 freescale semiconductor electrical characteristics note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in both the tables and figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? tx and rx refer to the transmit and receive sections of the ssi. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns table 67. ssi transmitter timing with external clock (continued) id parameter min max unit
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 95 4.9.9.4 ssi receiver timing with external clock figure 54 depicts the ssi receiver external clock timing and table 68 lists the timing parameters for the receiver timing with external clock. figure 54. ssi receiver external clock timing diagram table 68. ssi receiver timing with external clock id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss28 (rx) ck high to fs (bl) high ?10 15.0 ns ss30 (rx) ck high to fs (bl) low 10 ? ns ss32 (rx) ck high to fs (wl) high ?10 15.0 ns ss34 (rx) ck high to fs (wl) low 10 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10 ? ns ss41 srxd hold time after (rx) ck low 2 ? ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ss40 ss22 ss32 ss36 ss41 txc (input) txfs (bl) (input) txfs (wl) (input) rxd (input)
i.mx50 applications processors for consumer products, rev. 2 96 freescale semiconductor electrical characteristics note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in both the tables and figures. ? all timings are on audiomux pads when ssi is being used for data transfer. ? tx and rx refer to the transmit and receive sections of the ssi. ? the terms wl and bl refer to word length (wl) and bit length (bl). ? for internal frame sync operation using external clock, the fs timing is same as that of tx data (for example, during ac97 mode of operation). 4.9.10 uart i/o configuration and timing parameters the following sections describe the uart i/o configuration a nd timing parameters. 4.9.10.1 uart rs-232 i/o configuration in different modes table 69 shows the uart i/o configuration based on which mode is enabled. 4.9.10.2 uart rs-232 serial mode timing the following sections describe the electrical in formation of the uart module in the rs-232 mode. table 69. uart i/o configuration vs. mode port dte mode dce mode direction description direction description rts output rts from dte to dce input rts from dte to dce cts input cts from dce to dte output cts from dce to dte txd_mux input serial data from dce to dte output serial data from dce to dte rxd_mux output serial data from dte to dce input serial data from dte to dce
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 97 4.9.10.2.1 uart transmitter figure 55 depicts the transmit timing of uart in the rs-232 serial mode with 8 data bit/1 stop bit format. table 70 lists the uart rs-232 serial mode transmit timing characteristics. figure 55. uart rs-232 serial mode transmit timing diagram 4.9.10.2.2 uart receiver figure 56 depicts the rs-232 serial mode receive timing with 8 data bit/1 stop bit format. table 71 lists serial mode receive timing characteristics. figure 56. uart rs-232 serial mode receive timing diagram 4.9.10.3 uart irda mode timing the following sections give the uart transmit and receive timings in irda mode. table 70. rs-232 serial mode transmit timing parameters id parameter symbol min max units ua1 transmit bit time t tbit 1/f baud_rate 1 ?t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate +t ref_clk ? table 71. rs-232 serial mode receive timing parameters id parameter symbol min max units ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16*f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16*f baud_rate ). t rbit 1/f baud_rate 2 ? 1/(16*f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16*f baud_rate )? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2
i.mx50 applications processors for consumer products, rev. 2 98 freescale semiconductor electrical characteristics 4.9.10.3.1 uart irda mode transmitter figure 57 depicts the uart irda mode transmit timing with 8 data bit/1 stop bit format. table 72 lists the transmit timing characteristics. figure 57. uart irda mode transmit timing diagram 4.9.10.3.2 uart irda mode receiver figure 58 depicts the uart irda mode receive timing with 8 data bit/1 stop bit format. table 73 lists the receive timing characteristics. figure 58. uart irda mode receive timing diagram table 72. irda mode transmit timing parameters id parameter symbol min max units ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 ?t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16)*(1/f baud_rate ) ? t ref_clk (3/16)*(1/f baud_rate )+t ref_clk ? table 73. irda mode receive timing parameters id parameter symbol min. max. units ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16*f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16*f baud_rate ). t rirbit 1/f baud_rate 2 ?1/(16*f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate +1/(16*f baud_rate )? ua6 receive ir pulse duration t rirpulse 1.41 s (5/16)*(1/f baud_rate )? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit possible parity bit ua3 ua3 ua3 ua3 ua4 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit possible parity bit ua5 ua5 ua5 ua5 ua6
electrical characteristics i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 99 4.9.11 usb phy parameters this section describes the usb otg p hy and the usb host port phy parameters. 4.9.11.1 usb phy ac parameters table 74 lists the ac timing parameters for usb phy. 4.9.11.2 usb phy additional electrical parameters table 75 lists the parameters for additional electrical characteristics for usb phy. 4.9.11.3 usb phy system clocking (sysclk) table 76 lists the usb phy system clocking parameters table 74. usb phy ac timing parameters parameter conditions min typ max unit trise 1.5mbps 12mbps 480mbps 75 4 0.5 ? 300 20 ns tfall 1.5mbps 12mbps 480mbps 75 4 0.5 ? 300 20 ns jitter 1.5mbps 12mbps 480mbps ??10 1 0.2 ns table 75. additional electrical characteristics for usb phy parameter conditions min typ max unit vcm dc (dc level measured at receiver connector) hs mode ls/fs mode ?0.05 0.8 ?0.5 2.5 v crossover voltage ls mode fs mode 1.3 1.3 ?2 2 v power supply ripple noise (analog 3.3 v) < 160 mhz ?50 0 50 mv power supply ripple noise (analog 2.5 v) <1.2mhz >1.2mhz ?10 ?50 0 0 10 50 mv power supply ripple noise (digital 1.2 v) all conditions ?50 0 50 mv table 76. usb phy system clocking parameters parameter conditions min typ max unit clock deviation reference clock frequency 24 mhz ?150 ? 150 ppm rise/fall time ? ? ? 200 ps
i.mx50 applications processors for consumer products, rev. 2 100 freescale semiconductor package information and contact assignments 4.9.11.4 usb vbus parameters table 77 lists the usb vbus input parameters. 5 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 5.1 13 x 13 mm, 0.5 mm pitch, 416 pin mapbga package information this section contains the outline drawing, signal assignment map, ground, power, reference id (by ball grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin mapbga package. jitter (peak-peak) <1.2 mhz 0 ? 50 ps jitter (peak-peak) >1.2 mhz 0 ? 100 ps duty-cycle reference clock frequency 24 mhz 40 ? 60 % table 77. vbus comparators thresholds parameter conditions min typ max unit a-device session valid comparator threshold ? 0.8 1.4 2.0 v b-device session valid comparator threshold ? 0.8 1.4 4.0 v b-device session end comparator threshold ? 0.2 0.45 0.8 v vbus valid comparator threshold 1 1 for vbus maximum rating, see ta b l e 7 . ?4.44.64.75v vbus for chgr_det_b operation ? 3.0 ? ? v vbus input current vbus = 5.25 v ? ? 350 a table 76. usb phy system clocking parameters (continued) parameter conditions min typ max unit
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 101 5.1.1 case 416 mapbga, 13 x 13 mm, 0.5 mm pitch package views figure 59 shows the top view of the 13 x 13 mm package, figure 60 shows the bottom view (416 soldier balls) of the 13 x 13 mm package, and figure 61 shows the side view of the 13 x 13 mm package. figure 59. 416 mapbga 13x13 mm package top view figure 60. 416 mapbga 13x13 mm package bottom view
i.mx50 applications processors for consumer products, rev. 2 102 freescale semiconductor package information and contact assignments figure 61. 416 mapbga 13x13 mm package side view the following notes apply to figure 59 , figure 60 , and figure 61 : ? unless otherwise specified dimensions are in millimeters. ? all dimensions and tolerances conform to asme y14.5m-1994. ? parallelism measurement shall exclude any effect of mark on top surface of package.
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 103 5.1.2 416 mapbga 13 x 13 mm, 0.5 mm pitch ball map table 78 shows the 416 mapbga 13 x 13 mm, 0.5 mm pitch ball map. table 78. 416 mapbga 13x13 mm, 0.5 mm pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a vss eim_rdy eim_cre eim_eb0 eim_bclk eim_da12 eim_da8 eim_da4 eim_da0 epdc_sdshr epdc_gdclk epdc_gdrl epdc_sdclk epdc_d12 epdc_d8 epdc_d4 epdc_d0 vss dram_d30 dram_d29 nvcc_emi_dram dram_d26 dram_d25 vss a b key_col0 key_col1 eim_oe eim_eb1 eim_rw eim_da13 eim_da9 eim_da5 eim_da1 eim_cs0 epdc_gdoe epdc_gdsp epdc_sdclkn epdc_d13 epdc_d9 epdc_d5 epdc_d1 vss dram_d31 dram_d28 nvcc_emi_dram dram_d27 dram_d24 dram_dqm3 b c key_col2 key_col3 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdqs3 dram_sdqs3_b c d key_row0 key_row1 nc key_row2 eim_wait eim_da14 eim_da10 eim_da6 eim_da2 eim_cs1 epdc_sdce4 epdc_sdce2 epdc_sdce0 epdc_d14 epdc_d10 epdc_d6 epdc_d2 epdc_sdle epdc_sdoed epdc_vcom1 nvcc_emi_dram nc nvcc_emi_dram nvcc_emi_dram d e i2c1_scl i2c1_sda nc key_row3 eim_lba eim_da15 eim_da11 eim_da7 eim_da3 eim_cs2 epdc_sdce5 epdc_sdce3 epdc_sdce1 epdc_d15 epdc_d11 epdc_d7 epdc_d3 epdc_sdoe epdc_sdoez epdc_bdr0 epdc_bdr1 nc dram_d15 dram_d14 e f i2c2_scl i2c2_sda nc pwm2 pwm1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_a14 dram_a13 nc dram_d12 dram_d13 f g i2c3_scl i2c3_sda nc epito wdog nc owire vddgp vddgp vddgp epdc_pwrcom epdc_pwrctrl0 epdc_pwrctrl1 epdc_pwrctrl2 epdc_pwrctrl3 epdc_pwrstat epdc_vcom0 dram_sdodt0 nc vss vss nc vss dram_d10 g
i.mx50 applications processors for consumer products, rev. 2 104 freescale semiconductor package information and contact assignments h uart1_txd uart1_cts nc ssi_txfs ssi_txd nc ssi_rxfs vddgp vddgp vddgp vddgp vss vss vcc vcc vcc vcc dram_openfb nc dram_a12 dram_ras nc dram_d11 dram_d9 h j uart1_rxd uart1_rts nc ssi_txc ssi_rxd nc ssi_rxc vddgp nc nc nc nc nc nc nc nc vcc dram_open nc dram_a11 dram_cas nc dram_d8 dram_dqm1 j k uart2_txd uart2_cts nc uart3_txd uart4_txd nc vddgp vddgp nc vddgp vddgp vss vss vcc vcc nc vcc dram_sdba0 nc dram_a10 nvcc_emi_dram nc nvcc_emi_dram nvcc_emi_dram k l uart2_rxd uart2_rts nc uart3_rxd uart4_rxd nc nvcc_eim vddgp nc vddgp vddgp vss vss vss vcc nc vss dram_sdba1 nc dram_calibration dram_a9 nc dram_sdqs1 dram_sdqs1_b l m cspi_sclk cspi_mosi nc cspi_ss0 cspi_miso nc nvcc_eim nvcc_eim nc nvcc_epdc vss nc nc vss vss nc vss vss nc vss vss nc vref dram_sdclk_0_b m n ecspi1_sclk ecspi1_mosi nc ecspi2_ss0 ecspi2_miso nc ecspi1_miso nvcc_keypad nc nvcc_epdc vss nc nc vss vss nc vss dram_sdba2 nc dram_a7 dram_a8 nc vddo25 dram_sdclk_0 n p sd1_clk sd1_d1 nc ecspi2_sclk ecspi2_mosi nc ecspi1_ss0 nvcc_misc nc nvcc_epdc vss vss vss vss vddal1 nc vdda dram_sdwe nc dram_a5 dram_a6 nc dram_sdqs0 dram_sdqs0_b p table 78. 416 mapbga 13x13 mm, 0.5 mm pitch ball map (continued)
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 105 r sd1_cmd sd1_d0 nc sd1_d2 sd1_d3 nc nvcc_spi nvcc_ssi nc nvcc_epdc vss vss vss vss vddal1 nc vdda dram_sdodt1 nc dram_sdclk_1_b nvcc_emi_dram nc nvcc_emi_dram nvcc_emi_dram r t sd2_d0 sd2_d1 nc sd2_cd sd2_wp nc nvcc_sd1 nvcc_uart nc nc nc nc nc nc nc nc vss vss nc dram_sdclk_1 dram_cs0 nc dram_d6 dram_dqm0 t u sd2_clk sd2_d5 nc sd2_d6 sd2_d7 nc jtag_tdo nvcc_sd2 nvcc_jtag nvcc_epdc nvcc_lcd vss vss vss vss vss vss vss nc dram_sdcke dram_cs1 nc dram_d5 dram_d7 u v sd2_d2 sd2_d3 nc sd2_d4 sd2_cmd nc jtag_mod nvcc_reset nvcc_nandf nvcc_nandf chgr_det_b disp_d11 disp_d12 disp_d13 disp_d14 disp_d15 vss vss nc vss vss nc vss dram_d4 v w pmic_on_req pmic_stby_req nc jtag_tck gnd_dcdc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_a0 dram_a1 nc dram_d2 dram_d3 w y ckil eckil nc jtag_tms vdd_dcdco vdd_dcdci usb_otg_gpanaio usb_otg_id usb_otg_vbus usb_h1_vbus usb_h1_gpanaio disp_d1 disp_d3 disp_d5 disp_d7 disp_d9 disp_d10 sd3_d5 sd3_d7 dram_a2 dram_a3 nc dram_d1 dram_d0 y aa nvcc_srtc ngnd_srtc nc jtag_tdi jtag_trstb ckih gnd_kel usb_otg_rrefext vss usb_h1_rrefext vss disp_d0 disp_d2 disp_d4 disp_d6 disp_d8 sd3_d3 sd3_d4 sd3_d6 dram_a4 nvcc_emi_dram nc nvcc_emi_dram nvcc_emi_dram aa table 78. 416 mapbga 13x13 mm, 0.5 mm pitch ball map (continued)
i.mx50 applications processors for consumer products, rev. 2 106 freescale semiconductor package information and contact assignments 5.1.3 416 mapbga 13 x 13 power rails ab boot_mode0 boot_mode1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdqs2 dram_sdqs2_b ab ac reset_in_b test_mode gnd3p0 gnd2p5 extal gnd1p2 gnd1p8 usb_otg_dn usb_otg_vdda25_1 usb_h1_dn usb_h1_vdda33 disp_busy disp_rs disp_reset sd3_d0 sd3_d1 sd3_d2 vss dram_d16 dram_d18 nvcc_emi_dram dram_d20 dram_d22 dram_dqm2 ac ad vss por_b vdd3p0 vdd2p5 xtal vdd1p2 vdd1p8 usb_otg_dp usb_h1_vdda25_1 usb_h1_dp usb_otg_vdda33 disp_wr disp_rd disp_cs sd3_wp sd3_clk sd3_cmd vss dram_d17 dram_d19 nvcc_emi_dram dram_d21 dram_d23 vss ad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 table 79. 416 mapbga 13x13 ground, power, sense, and reference contact signals pin name ball number comments gnd_dcdc w5 ? nvcc_eim l7, m7, m8 ? nvcc_emi_dram a21, aa21, aa23, aa24, ac21, ad21, b21, d21, d23, d24, k21, k23, k24, r21, r23, r24 ? nvcc_epdc m10, n10, p10, r10, u10 ? nvcc_jtag u9 ? nvcc_keypad n8 ? nvcc_lcd u11 ? nvcc_misc p8 ? nvcc_nandf v9, v10 ? nvcc_reset v8 ? nvcc_sd1 t7 ? nvcc_sd2 u8 ? nvcc_spi r7 ? table 78. 416 mapbga 13x13 mm, 0.5 mm pitch ball map (continued)
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 107 nvcc_srtc aa1 ? nvcc_ssi r8 ? nvcc_uart t8 ? usb_h1_vdda25 ad9 note that on the 416 mapbga package, usb_otg_vdda25 and usb_h1_vdda25 are shorted together on the substrate. usb_h1_vdda33 ac11 note that on the 416 mapbga package, usb_otg_vdda33 and usb_h1_vdda33 are shorted together on the substrate. usb_otg_vdda25 ac9 note that on the 416 mapbga package, usb_otg_vdda25 and usb_h1_vdda25 are shorted together on the substrate. usb_otg_vdda33 ad11 note that on the 416 mapbga package, usb_otg_vdda33 and usb_h1_vdda33 are shorted together on the substrate. vcc h14, h15, h16, h17, j17, k14, k15, k17, l15 ? vdd_dcdci y6 ? vdd_dcdco y5 ? vdd1p2 ad6 ? vdd1p8 ad7 ? vdd2p5 ad4 ? vdd3p0 ad3 ? vdda p17, r17 ? vddal1 p15, r15 ? vddgp g10, g8, g9, h10, h11, h8, h9, j8, k10, k11, k7, k8, l10, l11, l8 ? vddo25 n23 ? vss a1, a18, a24, aa11, aa2, aa9, ac18, ac3, ac4, ac6, ac7, ad1, ad18, ad24, b18, g20, g21, g23, h12, h13, k12, k13, l12, l13, l14, l17, m11, m14, m15, m17, m18, m20, m21, n11, n14, n15, n17, p11, p12, p13, p14, r11, r12, r13, r14, t17, t18, u12, u13, u14, u15, u16, u17, u18, v17, v18, v20, v21, v23 ? table 79. 416 mapbga 13x13 ground, power, sense, and reference contact signals (continued)
i.mx50 applications processors for consumer products, rev. 2 108 freescale semiconductor package information and contact assignments 5.2 13 x 13 mm, 0.5 mm pitch, 416 pin popbga package information this section contains the outline drawing, signal assignment map, ground, power, reference id (by ball grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin popbga package. 5.2.1 416 popbga 13 x 13 mm package views figure shows the top view of the 416 popbga 13 x 13 package, figure 63 shows the side view of the package, and figure 64 shows the bottom view of the package. figure 62. 416 popbga 13 x 13 mm package top view
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 109 figure 63. 416 popbga 13 x 13 package side view figure 64. 416 popbga 13 x 13 mm package bottom view the following notes apply to figure , figure 63 , and figure 64 : ? unless otherwise specified dimensions are in millimeters.
i.mx50 applications processors for consumer products, rev. 2 110 freescale semiconductor package information and contact assignments ? all dimensions and tolerances conform to asme y14.5m-1994. ? parallelism measurement shall exclude any effect of mark on top surface of package. 5.2.2 416 popbga 13 x 13 mm, 0.5 pitch ball map table 80 shows the 416 popbga 13 x 13 mm ball map. table 80. 416 popbga 13 x 13 mm ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a vss uart1_rxd uart1_txd i2c3_scl i2c2_scl i2c1_scl key_row3 key_row0 key_col0 key_col1 eim_wait eim_bclk eim_da14 eim_da10 eim_da13 eim_da12 eim_da9 eim_da8 pop_emmc_rst pop_lpddr2_1.8v nvcc_emi_dram eim_da3 eim_da4 vss b uart2_txd uart2_cts uart1_rts uart1_cts i2c3_sda i2c2_sda i2c1_sda key_row1 key_col2 key_col3 eim_rdy eim_oe eim_lba eim_rw eim_da15 eim_da11 eim_da7 eim_da6 pop_lpddr2_1.8v pop_lpddr2_1.8v nvcc_emi_dram eim_da5 eim_da0 eim_cs0 c uart2_rxd uart2_rts nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc eim_da2 eim_da1 d sd2_d0 sd2_d1 nc uart3_txd uart4_rxd uart4_txd key_row2 epito wdog pwm2 pwm1 owire eim_cre eim_eb1 eim_eb0 eim_cs2 eim_cs1 epdc_sdce5 pop_nand_vcc pop_nand_vcc nvcc_emi_dram nc nvcc_emi_dram nvcc_emi_dram e sd2_clk sd2_d5 nc uart3_rxd nvcc_emi_dram nvcc_emi_dram nvcc_emi_dram vss vss dram_d31 dram_d30 dram_d29 dram_d28 dram_d26 dram_d25 dram_sdqs3 vss vss dram_d15 dram_d14 vss nc epdc_pwrcom epdc_pwrctrl0 f sd2_d2 sd2_d3 nc sd2_d7 nvcc_emi_dram nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d13 vss nc epdc_pwrctrl2 epdc_pwrstat
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 111 g sd2_cmd sd2_d4 nc sd2_wp nvcc_emi_dram nc nvcc_emi_dram vddgp vddgp vddgp vss vss vss dram_d27 dram_d24 dram_sdqs3_b dram_dqm3 dram_d12 nc dram_d10 vss nc vss epdc_gdclk h cspi_sclk cspi_miso nc sd2_d6 dram_a9 nc vddgp vddgp vddgp vddgp vss vss vss vcc vcc vcc vcc dram_d11 nc dram_d9 epdc_sdce2 nc epdc_sdshr epdc_vcom0 j cspi_mosi cspi_ss0 nc sd2_cd dram_a8 nc vddgp vddgp nc nc nc nc nc nc nc nc vcc dram_d8 nc dram_sdqs1 epdc_sdce3 nc epdc_d12 epdc_gdoe k ecspi2_ss0 ecspi2_mosi nc ecspi1_miso dram_a7 nc vddgp vddgp nc vddgp vss vss vss vcc vcc nc vcc dram_sdqs1_b nc nvcc_emi_dram epdc_sdce4 nc epdc_pwrctrl1 epdc_sdclk l ecspi2_sclk ecspi2_miso nc ecspi1_ss0 dram_a6 nc vddgp vddgp nc vddgp vss vss vss vss vcc nc vss dram_dqm1 nc nvcc_emi_dram epdc_pwrctrl3 nc epdc_gdrl epdc_sdclkn m sd1_clk sd1_d2 nc ecspi1_sclk pop_lpddr2_1.8v nc nvcc_eim nvcc_eim nc nvcc_epdc vss nc nc vss vss nc vss dram_dqm0 nc nvcc_emi_dram epdc_d13 nc vref epdc_sdle n sd1_cmd sd1_d1 nc ecspi1_mosi pop_lpddr2_1.8v nc nvcc_eim nvcc_keypad nc nvcc_epdc vss nc nc vss vss nc vss dram_sdqs0 nc nvcc_emi_dram epdc_d14 nc vddo25 epdc_sdce0 table 80. 416 popbga 13 x 13 mm ball map (continued)
i.mx50 applications processors for consumer products, rev. 2 112 freescale semiconductor package information and contact assignments p sd3_d4 sd1_d0 nc dram_calibration dram_sdclk_0_b nc dram_a5 nvcc_misc nc nvcc_epdc vss vss vss vss vddal1 nc vdda dram_sdqs0_b nc nvcc_emi_dram epdc_d15 nc epdc_gdsp epdc_sdce1 r sd3_d2 sd3_d6 nc sd1_d3 dram_sdclk_0 nc nvcc_spi nvcc_ssi nc nvcc_epdc vss vss vss vss vddal1 nc vdda dram_d7 nc nvcc_emi_dram epdc_d11 nc epdc_sdoed epdc_d4 t sd3_clk sd3_cmd nc sd3_wp dram_sdcke nc nvcc_sd1 nvcc_uart nc nc nc nc nc nc nc nc vss dram_d6 nc dram_d4 epdc_d9 nc epdc_d7 epdc_d5 u sd3_d5 sd3_d3 nc sd3_d7 dram_cs0 nc dram_cs1 nvcc_sd2 nvcc_jtag nvcc_epdc nvcc_lcd vss vss vss vss vss vss dram_d5 nc dram_d3 epdc_sdoez nc epdc_d2 epdc_d6 v sd3_d0 sd3_d1 nc jtag_tdo jtag_mod nc dram_a0 nvcc_reset nvcc_nandf nvcc_nandf dram_d16 dram_d18 dram_d20 dram_d22 dram_sdqs2_b dram_d0 dram_d2 nvcc_emi_dram nc nvcc_emi_dram epdc_sdoe nc epdc_d10 epdc_d3 w pmic_on_req pmic_stby_req nc jtag_tck gnd_dcdc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nvcc_emi_dram epdc_vcom1 nc epdc_d8 epdc_d1 y ckil eckil nc jtag_tms vdd_dcdco vdd_dcdci dram_a1 dram_a2 dram_a3 dram_a4 dram_d17 dram_d19 dram_d21 dram_d23 dram_sdqs2 dram_dqm2 dram_d1 nvcc_emi_dram nvcc_emi_dram nvcc_emi_dram epdc_bdr0 nc epdc_bdr1 epdc_d0 table 80. 416 popbga 13 x 13 mm ball map (continued)
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 113 5.2.3 416 popbga 13 x 13 mm power rails table 81 shows the device connection list for ground, power, sense, and reference contact signals. table 84 displays an alpha-sorted list of the signal assignments including power rails and associated power supplies. aa nvcc_srtc vss nc jtag_tdi jtag_trstb ckih gnd_kel usb_otg_rrefext vss usb_h1_rrefext vss usb_otg_id usb_otg_vbus usb_otg_gpanaio chgr_det_b usb_h1_vbus usb_h1_gpanaio vss disp_reset disp_rd disp_busy nc pop_lpddr2_zq1 pop_lpddr2_zq0 ab boot_mode0 boot_mode1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc disp_d14 disp_d5 ac reset_in_b test_mode vss vss extal vss vss usb_otg_dn usb_vdda25 usb_h1_dn usb_vdda33 ssi_txfs ssi_txc ssi_rxd disp_d3 disp_d1 disp_d0 vss disp_d7 disp_d9 disp_cs disp_d12 disp_d13 disp_d4 ad vss por_b vdd3p0 vdd2p5 xtal vdd1p2 vdd1p8 usb_otg_dp usb_vdda25 usb_h1_dp usb_vdda33 ssi_rxc ssi_rxfs ssi_txd disp_d2 disp_d6 disp_ vss disp_d11 disp_wr disp_d15 disp_d10 disp_rs vss table 81. 416 popbga 13 x 13 mm ground, power, sense, and reference contact signals pin name ball number comments gnd_dcdc w5 ? nvcc_eim n7 m7 m8 ? nvcc_emi_dram a21, b21, d21, d23, d24, e5, e6, e7, f5, g5, g7, k20, l20, m20, n20, p20, r20, v18, v20, w20, y18, y19, y20 these are the 1.2v supply to both the i.mx50 dram controller as well as the pop lpddr2. nvcc_epdc m10, n10, p10, r10, u10 ? nvcc_jtag u9 ? nvcc_keypad n8 ? nvcc_lcd u11 ? nvcc_misc p8 ? nvcc_nandf v9, v10 ? table 80. 416 popbga 13 x 13 mm ball map (continued)
i.mx50 applications processors for consumer products, rev. 2 114 freescale semiconductor package information and contact assignments nvcc_reset v8 ? nvcc_sd1 t7 ? nvcc_sd2 u8 ? nvcc_spi r7 ? nvcc_srtc aa1 ? nvcc_ssi r8 ? nvcc_uart t8 ? pop_emmc_rst a19 this is pop emmc 4.4 nand reset input pin. this pin does not connect to the i.mx50. if using emmc 4.4 nand, this pin can be connected to a gpio. for non 4.4 emmc applications, leave floating. pop_lpddr2_1.8v a20, b19, b20, m5, n5 this is the 1.8v supply for the pop lpddr2. these pins do not connect to the i.mx50. pop_lpddr2_zq0 aa24 this is the pop lpddr2 zq0 pin. this pin does not connect to the i.mx50. this should be connected on the pcb to a 240 1% resistor to ground pop_lpddr2_zq1 aa23 this is the pop lpddr2 zq1 pin. this pin does not connect to the i.mx50. if used, this should be connected on the pcb to a 240 1% resistor to ground pop_nand_vcc d19, d20 this is the 3.3v i/o and memory supply for the pop emmc nand. note that because the emmc memory and i/o domains are shorted together, it is not possible to support 1.8 v i/o for the pop emmc nand. usb_vdda25 ac9, ad9 note that on the popbga package, usb_otg_vdda25 and usb_h1_vdda25 are shorted together. usb_vdda33 ac11, ad11 note that on the popbga package, usb_otg_vdda33 and usb_h1_vdda33 are shorted together. vcc h14, h15, h16, h17, j17, k14, k15, k17, l15 ? vdd_dcdci y6 ? vdd_dcdco y5 ? vdd1p2 ad6 ? vdd1p8 ad7 ? table 81. 416 popbga 13 x 13 mm ground, power, sense, and reference contact signals (continued)
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 115 5.3 17 x 17 mm, 0.8 mm pitch, 400 pin mapbga package information this section contains the outline drawing, signal assignment map, ground, power, reference id (by ball grid location) for the 17 x 17 mm, 0.8 mm pitch, 400 pin mapbga package. vdd2p5 ad4 ? vdd3p0 ad3 ? vdda p17, r17 ? vddal1 p15, r15 ? vddgp g10, g8, g9, h10, h7, h8, h9, j7, j8, k10, k7, k8, l10, l7, l8 ? vddo25 n23 ? vss a1, a24, aa11, aa18, aa2, aa9, ac18, ac3, ac4, ac6, ac7, ad1, ad18, ad24, e17, e18, e21, e8, e9, f21, g11, g12, g13, g21, g23, h11, h12, h13, k11, k12, k13, l11, l12, l13, l14, l17, m11, m14, m15, m17, n11, n14, n15, n17, p11, p12, p13, p14, r11, r12, r13, r14, t17, u12, u13, u14, u15, u16, u17 ? table 81. 416 popbga 13 x 13 mm ground, power, sense, and reference contact signals (continued)
i.mx50 applications processors for consumer products, rev. 2 116 freescale semiconductor package information and contact assignments 5.3.1 400 mapbga 17 x 17 mm package views figure 65 shows the top view of the 17 x 17 mm package, figure 66 shows the bottom view of the package, and figure 67 shows the side view of the package. figure 65. 400 mapbga 17x17 mm package top view 17 a1 index area 17 b c 0.15 top view 4x
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 117 figure 66. 400 mapbga 17x17 mm package bottom view
i.mx50 applications processors for consumer products, rev. 2 118 freescale semiconductor package information and contact assignments figure 67. 400 mapbga 17x17 mm package side view the following notes apply to figure 65 , figure 66 , and figure 67 : ? unless otherwise specified dimensions are in millimeters. ? all dimensions and tolerances conform to asme y14.5m-1994. ? parallelism measurement shall exclude any effect of mark on top surface of package. 5.3.2 400 mapbga 17 x 17 mm ball map table 82 shows the 400 mapbga 17 x 17 mm ball map. table 82. 400 mapbga 17 x 17 mm ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a nc eim_rdy eim_cre eim_eb0 eim_bclk eim_da12 eim_da8 epdc_sdshr eim_da4 epdc_gdrl epdc_gdclk epdc_sdce1 epdc_d5 epdc_d1 epdc_bdr0 dram_d26 dram_d28 dram_d29 dram_d30 nc b key_col0 key_col1 eim_oe eim_eb1 eim_rw eim_da13 eim_da9 eim_da5 eim_da1 eim_da0 eim_cs0 epdc_sdce0 epdc_sdclk epdc_vcom0 epdc_d0 epdc_d2 dram_d27 dram_d25 dram_d24 dram_d31
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 119 c key_col2 key_col3 key_row2 eim_wait eim_da14 eim_da10 eim_da6 eim_da2 eim_cs1 epdc_gdoe epdc_sdce2 epdc_pwrstat epdc_sdoe epdc_d6 epdc_sdle epdc_d3 dram_d15 dram_d14 dram_sdqs3 dram_sdqs3_b d key_row0 key_row1 key_row3 eim_lba eim_da15 eim_da11 eim_da7 eim_da3 eim_cs2 epdc_sdce4 epdc_gdsp epdc_sdclkn epdc_d10 epdc_d7 epdc_d4 epdc_bdr1 dram_d8 dram_d12 dram_d11 dram_dqm3 e i2c1_scl i2c1_sda pwm2 pwm1 owire epdc_sdce5 epdc_pwrcom epdc_sdce3 epdc_pwrctrl1 epdc_pwrctrl0 epdc_d14 epdc_pwrctrl2 epdc_d15 epdc_d13 epdc_d8 epdc_d9 dram_d10 dram_d13 dram_a12 dram_ras f i2c2_scl i2c2_sda ssi_rxd wdog epito nvcc_eim nvcc_eim nvcc_eim nvcc_epdc nvcc_epdc nvcc_epdc nvcc_epdc epdc_d12 epdc_d11 epdc_pwrctrl3 epdc_sdoez dram_dqm1 dram_d9 dram_a13 dram_calibration g i2c3_scl i2c3_sda ssi_txc ssi_txd ssi_rxfs vddgp vddgp vddgp vddgp vddgp vss vss vss vss epdc_vcom1 epdc_sdoed dram_sdqs1 dram_sdqs1_b dram_a9 dram_cas h uart1_txd uart4_txd ssi_txfs ssi_rxc nvcc_keypad vddgp vddgp vddgp vddgp vddgp vss vss vss vss vss nvcc_emi_dram dram_openfb dram_open dram_a11 dram_sdba1 j uart1_cts uart3_txd uart4_rxd cspi_ss0 nvcc_misc vddgp vddgp vss vddal1 vddal1 vdda vcc vss vss nvcc_emi_dram nvcc_emi_dram dram_sdclk_0 dram_sdclk_0_b dram_a10 dram_sdba0 table 82. 400 mapbga 17 x 17 mm ball map (continued)
i.mx50 applications processors for consumer products, rev. 2 120 freescale semiconductor package information and contact assignments k uart1_rxd uart1_rts uart3_rxd cspi_miso nvcc_ssi vddgp vddgp vss vdda vcc vcc vcc vss nvcc_emi_dram nvcc_emi_dram nvcc_emi_dram vref dram_sdodt0 dram_a5 dram_a7 l uart2_txd uart2_rxd cspi_mosi ecspi2_miso nvcc_uart vddgp vss vss vss vcc vcc vcc vss vss nvcc_emi_dram nvcc_emi_dram vddo25 dram_sdwe dram_a6 dram_a8 m cspi_sclk ecspi2_ss0 ecspi1_miso ecspi1_mosi nvcc_spi vss vss vss vss vcc vcc vss vss vss vss nvcc_emi_dram dram_sdqs0 dram_sdqs0_b dram_sdba2 dram_d6 n ecspi2_mosi ecspi1_sclk ecspi1_ss0 ecspi2_sclk nvcc_sd1 vss vss vss vss vss vss vss vss nvcc_emi_dram nvcc_emi_dram nvcc_emi_dram dram_dqm0 dram_d5 dram_d7 dram_d4 p sd1_d1 sd1_d3 sd1_d2 sd1_cmd nvcc_sd2 nvcc_reset vss vss nvcc_jtag nvcc_lcd nvcc_nandf nvcc_nandf vss vss nvcc_emi_dram nvcc_emi_dram dram_cs0 dram_cs1 dram_d3 dram_d2 r sd1_clk sd1_d0 sd2_d0 sd2_d6 nvcc_srtc gnd_dcdc vdd_dcdci jtag_tck jtag_tms vss vss vss vss vss vss nvcc_emi_dram dram_a4 dram_sdcke dram_d1 dram_d0 t sd2_cd sd2_wp sd2_clk sd2_d3 vss vdd_dcdco gnd_kel jtag_mod jtag_tdo chgr_det_b disp_d1 disp_cs disp_d13 disp_reset sd3_d7 sd3_d2 dram_a0 dram_a1 dram_sdqs2 dram_sdqs2_b table 82. 400 mapbga 17 x 17 mm ball map (continued)
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 121 u sd2_d1 sd2_d5 boot_mode1 test_mode vdd3p0 vdd1p2 jtag_trstb jtag_tdi usb_h1_rrefext usb_h1_gpanaio disp_busy disp_d6 disp_d5 disp_d14 sd3_d3 sd3_cmd sd3_d5 dram_a2 dram_d23 dram_dqm2 v sd2_cmd sd2_d4 boot_mode0 ckih vdd2p5 vdd1p8 usb_otg_gpanaio usb_otg_vbus usb_h1_vbus disp_wr disp_d0 disp_rd disp_d7 disp_d12 disp_d9 sd3_d1 sd3_d6 dram_a3 dram_d18 dram_d22 w sd2_d7 sd2_d2 reset_in_b eckil vss extal usb_otg_rrefext usb_otg_dn usb_otg_vdda25 usb_h1_dn usb_h1_vdda33 disp_d2 disp_d3 disp_d11 disp_d8 sd3_wp sd3_d4 dram_d21 dram_d19 dram_d20 y nc pmic_stby_req pmic_on_req ckil por_b xtal usb_otg_id usb_otg_dp usb_h1_vdda25 usb_h1_dp usb_otg_vdda33 disp_rs disp_d4 sd3_clk disp_d15 disp_d10 sd3_d0 dram_d17 dram_d16 nc table 82. 400 mapbga 17 x 17 mm ball map (continued)
i.mx50 applications processors for consumer products, rev. 2 122 freescale semiconductor package information and contact assignments 5.3.3 400 mapbga 17 x 17 power rails table 83. 400 mapbga 17x17 ground, power, sense, and reference contact signals pin name ball number nc a1 y1 a20 y20 nvcc_eim f6 f7 f8 nvcc_emi_dram k14 n14 j15 k15 l15 n15 p15 h16 j16 k16 l16 m16 n16 p16 r16 nvcc_epdc f9 f10 f11 f12 nvcc_jtag p9 nvcc_keypad h5 nvcc_lcd p10 nvcc_misc j5 nvcc_nandf p11 p12 nvcc_reset p6 nvcc_sd1 n5 nvcc_sd2 p5 nvcc_spi m5 nvcc_srtc r5 nvcc_ssi k5 nvcc_uart l5 usb_h1_vdda25 y9 usb_h1_vdda33 w11 usb_otg_vdda25 w9 usb_otg_vdda33 y11 vcc k10 l10 m10 k11 l11 m11 j12 k12 l12 vdd1p2 u6 vdd1p8 v6 vdd2p5 v5 vdd3p0 u5 vdda k9 j11 vddal1 j9 j10 vddgp g6 h6 j6 k6 l6 g7 h7 j7 k7 g8 h8 g9 h9 g10 h10 vddo25 l17 vss t5 w5 m6 n6 l7 m7 n7 p7 j8 k8 l8 m8 n8 p8 l9 m9 n9 n10 r10 g11 h11 n11 r11 g12 h12 m12 n12 r12 g13 h13 j13 k13 l13 m13 n13 p 13 r13 g14 h14 j14 l14 m14 p14 r14 h15 m15 r15
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 123 5.4 signal assignments vdd_dcdci r7 vdd_dcdco t6 gnd_dcdc r6 table 84. alphabetical list of signal assignments pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset boot_mode0 ab1 ab1 v3 nvcc_reset lvio alt0 in 100k pu boot_mode1 ab2 ab2 u3 nvcc_reset lvio alt0 in 100k pu chgr_det_b v11 aa15 t10 usb_h1_vdda25, usb_h1_vdda33 analog25 ? out-od ? ckih aa6 aa6 v4 nvcc_jtag analog ? ? ? ckil y1 y1 y4 nvcc_srtc analog ? ? ? cspi_miso m5 h2 k4 nvcc_spi hvio alt1 in keeper cspi_mosi m2 j1 l3 nvcc_spi hvio alt1 in keeper cspi_sclk m1 h1 m1 nvcc_spi hvio alt1 in keeper cspi_ss0 m4 j2 j4 nvcc_spi hvio alt1 in keeper disp_busy ac12 aa21 u11 nvcc_lcd hvio alt1 in keeper disp_cs ad14 ac21 t12 nvcc_lcd hvio alt3 out-lo 100k pu disp_d0 aa12 ac17 v11 nvcc_lcd hvio alt3 out-lo 100k pu disp_d1 y12 ac16 t11 nvcc_lcd hvio alt3 out-lo 100k pu disp_d10 y17 ad22 y16 nvcc_nandf hvio alt1 in keeper disp_d11 v12 ad19 w14 nvcc_nandf hvio alt1 in keeper disp_d12 v13 ac22 v14 nvcc_nandf hvio alt1 in keeper disp_d13 v14 ac23 t13 nvcc_nandf hvio alt1 in keeper disp_d14 v15 ab23 u14 nvcc_nandf hvio alt1 in keeper disp_d15 v16 ad21 y15 nvcc_nandf hvio alt1 in keeper disp_d2 aa13 ad15 w12 nvcc_lcd hvio alt3 out-lo 100k pu disp_d3 y13 ac15 w13 nvcc_lcd hvio alt3 out-lo 100k pu disp_d4 aa14 ac24 y13 nvcc_lcd hvio alt3 out-lo 100k pu disp_d5 y14 ab24 u13 nvcc_lcd hvio alt3 out-lo 100k pu table 83. 400 mapbga 17x17 ground, power, sense, and reference contact signals (continued)
i.mx50 applications processors for consumer products, rev. 2 124 freescale semiconductor package information and contact assignments disp_d6 aa15 ad16 u12 nvcc_lcd hvio alt3 out-lo 100k pu disp_d7 y15 ac19 v13 nvcc_lcd hvio alt3 out-lo 100k pu disp_d8 aa16 ad17 w15 nvcc_nandf hvio alt1 in keeper disp_d9 y16 ac20 v15 nvcc_nandf hvio alt1 in keeper disp_rd ad13 aa20 v12 nvcc_lcd hvio alt3 out-lo 100k pu disp_reset ac14 aa19 t14 nvcc_lcd hvio alt1 in keeper disp_rs ac13 ad23 y12 nvcc_lcd hvio alt3 out-lo 100k pu disp_wr ad12 ad20 v10 nvcc_lcd hvio alt3 out-lo 100k pu dram_a0 w20 v7 t17 nvcc_emi_dram dram alt0 out-lo keeper dram_a1 w21 y7 t18 nvcc_emi_dram dram alt0 out-lo keeper dram_a10 k20 ? j19 nvcc_emi_dram dram alt0 out-lo keeper dram_a11 j20 ? h19 nvcc_emi_dram dram alt0 out-lo keeper dram_a12 h20 ? e19 nvcc_emi_dram dram alt0 out-lo keeper dram_a13 f21 ? f19 nvcc_emi_dram dram alt0 out-lo keeper dram_a14 f20 ? ? nvcc_emi_dram dram alt0 out-lo keeper dram_a2 y20 y8 u18 nvcc_emi_dram dram alt0 out-lo keeper dram_a3 y21 y9 v18 nvcc_emi_dram dram alt0 out-lo keeper dram_a4 aa20 y10 r17 nvcc_emi_dram dram alt0 out-lo keeper dram_a5 p20 p7 k19 nvcc_emi_dram dram alt0 out-lo keeper dram_a6 p21 l5 l19 nvcc_emi_dram dram alt0 out-lo keeper dram_a7 n20 k5 k20 nvcc_emi_dram dram alt0 out-lo keeper dram_a8 n21 j5 l20 nvcc_emi_dram dram alt0 out-lo keeper dram_a9 l21 h5 g19 nvcc_emi_dram dram alt0 out-lo keeper dram_calibrati on l20 p4 f20 nvcc_emi_dram dramcali b ?? ? dram_cas j21 ? g20 nvcc_emi_dram dram alt0 out-hi keeper dram_cs0 t21 u5 p17 nvcc_emi_dram dram alt0 out-hi keeper dram_cs1 u21 u7 p18 nvcc_emi_dram dram alt0 out-hi keeper dram_d0 y24 v16 r20 nvcc_emi_dram dram alt0 in keeper dram_d1 y23 y17 r19 nvcc_emi_dram dram alt0 in keeper table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 125 dram_d10 g24 g20 e17 nvcc_emi_dram dram alt0 in keeper dram_d11 h23 h18 d19 nvcc_emi_dram dram alt0 in keeper dram_d12 f23 g18 d18 nvcc_emi_dram dram alt0 in keeper dram_d13 f24 f20 e18 nvcc_emi_dram dram alt0 in keeper dram_d14 e24 e20 c18 nvcc_emi_dram dram alt0 in keeper dram_d15 e23 e19 c17 nvcc_emi_dram dram alt0 in keeper dram_d16 ac19 v11 y19 nvcc_emi_dram dram alt0 in keeper dram_d17 ad19 y11 y18 nvcc_emi_dram dram alt0 in keeper dram_d18 ac20 v12 v19 nvcc_emi_dram dram alt0 in keeper dram_d19 ad20 y12 w19 nvcc_emi_dram dram alt0 in keeper dram_d2 w23 v17 p20 nvcc_emi_dram dram alt0 in keeper dram_d20 ac22 v13 w20 nvcc_emi_dram dram alt0 in keeper dram_d21 ad22 y13 w18 nvcc_emi_dram dram alt0 in keeper dram_d22 ac23 v14 v20 nvcc_emi_dram dram alt0 in keeper dram_d23 ad23 y14 u19 nvcc_emi_dram dram alt0 in keeper dram_d24 b23 g15 b19 nvcc_emi_dram dram alt0 in keeper dram_d25 a23 e15 b18 nvcc_emi_dram dram alt0 in keeper dram_d26 a22 e14 a16 nvcc_emi_dram dram alt0 in keeper dram_d27 b22 g14 b17 nvcc_emi_dram dram alt0 in keeper dram_d28 b20 e13 a17 nvcc_emi_dram dram alt0 in keeper dram_d29 a20 e12 a18 nvcc_emi_dram dram alt0 in keeper dram_d3 w24 u20 p19 nvcc_emi_dram dram alt0 in keeper dram_d30 a19 e11 a19 nvcc_emi_dram dram alt0 in keeper dram_d31 b19 e10 b20 nvcc_emi_dram dram alt0 in keeper dram_d4 v24 t20 n20 nvcc_emi_dram dram alt0 in keeper dram_d5 u23 u18 n18 nvcc_emi_dram dram alt0 in keeper dram_d6 t23 t18 m20 nvcc_emi_dram dram alt0 in keeper dram_d7 u24 r18 n19 nvcc_emi_dram dram alt0 in keeper dram_d8 j23 j18 d17 nvcc_emi_dram dram alt0 in keeper dram_d9 h24 h20 f18 nvcc_emi_dram dram alt0 in keeper table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
i.mx50 applications processors for consumer products, rev. 2 126 freescale semiconductor package information and contact assignments dram_dqm0 t24 m18 n17 nvcc_emi_dram dram alt0 in keeper dram_dqm1 j24 l18 f17 nvcc_emi_dram dram alt0 in keeper dram_dqm2 ac24 y16 u20 nvcc_emi_dram dram alt0 in keeper dram_dqm3 b24 g17 d20 nvcc_emi_dram dram alt0 in keeper dram_open j18 ? h18 nvcc_emi_dram dram alt0 out-lo keeper dram_openfb h18 ? h17 nvcc_emi_dram dram alt0 in keeper dram_ras h21 ? e20 nvcc_emi_dram dram alt0 out-hi keeper dram_sdba0 k18 ? j20 nvcc_emi_dram dram alt0 out-lo keeper dram_sdba1 l18 ? h20 nvcc_emi_dram dram alt0 out-lo keeper dram_sdba2 n18 ? m19 nvcc_emi_dram dram alt0 out-lo keeper dram_sdcke u20 t5 r18 nvcc_emi_dram dram alt0 out-lo keeper dram_sdclk_0 n24 r5 j17 nvcc_emi_dram dramclk alt0 out-lo keeper dram_sdclk_0_ b m24 p5 j18 nvcc_emi_dram dramclk alt0 out-hi ? dram_sdclk_1 t20 ? ? nvcc_emi_dram dramclk alt0 out-lo keeper dram_sdclk_1_ b r20 ? ? nvcc_emi_dram dramclk alt0 out-hi ? dram_sdodt0 g18 ? k18 nvcc_emi_dram dram alt0 out-lo keeper dram_sdodt1 r18 ? ? nvcc_emi_dram dram alt0 out-lo keeper dram_sdqs0 p23 n18 m17 nvcc_emi_dram dramclk alt0 in ? dram_sdqs0_b p24 p18 m18 nvcc_emi_dram dramclk alt0 in ? dram_sdqs1 l23 j20 g17 nvcc_emi_dram dramclk alt0 in ? dram_sdqs1_b l24 k18 g18 nvcc_emi_dram dramclk alt0 in ? dram_sdqs2 ab23 y15 t19 nvcc_emi_dram dramclk alt0 in ? dram_sdqs2_b ab24 v15 t20 nvcc_emi_dram dramclk alt0 in ? dram_sdqs3 c23 e16 c19 nvcc_emi_dram dramclk alt0 in ? dram_sdqs3_b c24 g16 c20 nvcc_emi_dram dramclk alt0 in ? dram_sdwe p18 ? l18 nvcc_emi_dram dram alt0 out-hi keeper eckil y2 y2 w4 nvcc_srtc analog ? ? ? ecspi1_miso n7 k4 m3 nvcc_spi hvio alt1 in keeper ecspi1_mosi n2 n4 m4 nvcc_spi hvio alt1 in keeper table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 127 ecspi1_sclk n1 m4 n2 nvcc_spi hvio alt1 in keeper ecspi1_ss0 p7 l4 n3 nvcc_spi hvio alt1 in keeper ecspi2_miso n5 l2 l4 nvcc_spi hvio alt1 in keeper ecspi2_mosi p5 k2 n1 nvcc_spi hvio alt1 in keeper ecspi2_sclk p4 l1 n4 nvcc_spi hvio alt1 in keeper ecspi2_ss0 n4 k1 m2 nvcc_spi hvio alt1 in keeper eim_bclk a5 a12 a5 nvcc_eim hvio alt0 out-lo 100k pu eim_cre a3 d13 a3 nvcc_eim hvio alt0 out-lo 100k pu eim_cs0 b10 b24 b11 nvcc_eim hvio alt0 out-hi 100k pu eim_cs1 d10 d17 c9 nvcc_eim hvio alt0 out-hi 100k pu eim_cs2 e10 d16 d9 nvcc_eim hvio alt0 out-hi 100k pu eim_da0 a9 b23 b10 nvcc_eim hvio alt0 in 100k pu eim_da1 b9 c24 b9 nvcc_eim hvio alt0 in 100k pu eim_da10 d7 a14 c6 nvcc_eim hvio alt0 in 100k pu eim_da11 e7 b16 d6 nvcc_eim hvio alt0 in 100k pu eim_da12 a6 a16 a6 nvcc_eim hvio alt0 in 100k pu eim_da13 b6 a15 b6 nvcc_eim hvio alt0 in 100k pu eim_da14 d6 a13 c5 nvcc_eim hvio alt0 in 100k pu eim_da15 e6 b15 d5 nvcc_eim hvio alt0 in 100k pu eim_da2 d9 c23 c8 nvcc_eim hvio alt0 in 100k pu eim_da3 e9 a22 d8 nvcc_eim hvio alt0 in 100k pu eim_da4 a8 a23 a9 nvcc_eim hvio alt0 in 100k pu eim_da5 b8 b22 b8 nvcc_eim hvio alt0 in 100k pu eim_da6 d8 b18 c7 nvcc_eim hvio alt0 in 100k pu eim_da7 e8 b17 d7 nvcc_eim hvio alt0 in 100k pu eim_da8 a7 a18 a7 nvcc_eim hvio alt0 in 100k pu eim_da9 b7 a17 b7 nvcc_eim hvio alt0 in 100k pu eim_eb0 a4 d15 a4 nvcc_eim hvio alt0 out-hi 100k pu eim_eb1 b4 d14 b4 nvcc_eim hvio alt0 out-hi 100k pu eim_lba e5 b13 d4 nvcc_eim hvio alt0 out-hi 100k pu table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
i.mx50 applications processors for consumer products, rev. 2 128 freescale semiconductor package information and contact assignments eim_oe b3 b12 b3 nvcc_eim hvio alt0 out-hi 100k pu eim_rdy a2 b11 a2 nvcc_eim hvio alt0 in 100k pu eim_rw b5 b14 b5 nvcc_eim hvio alt0 out-hi 100k pu eim_wait d5 a11 c4 nvcc_eim hvio alt0 in 100k pu epdc_bdr0 e20 y21 a15 nvcc_epdc hvio alt1 in keeper epdc_bdr1 e21 y23 d16 nvcc_epdc hvio alt1 in keeper epdc_d0 a17 y24 b15 nvcc_epdc hvio alt1 in keeper epdc_d1 b17 w24 a14 nvcc_epdc hvio alt1 in keeper epdc_d10 d15 v23 d13 nvcc_epdc hvio alt1 in keeper epdc_d11 e15 r21 f14 nvcc_epdc hvio alt1 in keeper epdc_d12 a14 j23 f13 nvcc_epdc hvio alt1 in keeper epdc_d13 b14 m21 e14 nvcc_epdc hvio alt1 in keeper epdc_d14 d14 n21 e11 nvcc_epdc hvio alt1 in keeper epdc_d15 e14 p21 e13 nvcc_epdc hvio alt1 in keeper epdc_d2 d17 u23 b16 nvcc_epdc hvio alt1 in keeper epdc_d3 e17 v24 c16 nvcc_epdc hvio alt1 in keeper epdc_d4 a16 r24 d15 nvcc_epdc hvio alt1 in keeper epdc_d5 b16 t24 a13 nvcc_epdc hvio alt1 in keeper epdc_d6 d16 u24 c14 nvcc_epdc hvio alt1 in keeper epdc_d7 e16 t23 d14 nvcc_epdc hvio alt1 in keeper epdc_d8 a15 w23 e15 nvcc_epdc hvio alt1 in keeper epdc_d9 b15 t21 e16 nvcc_epdc hvio alt1 in keeper epdc_gdclk a11 g24 a11 nvcc_epdc hvio alt1 in keeper epdc_gdoe b11 j24 c10 nvcc_epdc hvio alt1 in keeper epdc_gdrl a12 l23 a10 nvcc_epdc hvio alt1 in keeper epdc_gdsp b12 p23 d11 nvcc_epdc hvio alt1 in keeper epdc_pwrcom g11 e23 e7 nvcc_epdc hvio alt1 in keeper epdc_pwrctrl 0 g12 e24 e10 nvcc_epdc hvio alt1 in keeper epdc_pwrctrl 1 g13 k23 e9 nvcc_epdc hvio alt1 in keeper table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 129 epdc_pwrctrl 2 g14 f23 e12 nvcc_epdc hvio alt1 in keeper epdc_pwrctrl 3 g15 l21 f15 nvcc_epdc hvio alt1 in keeper epdc_pwrstat g16 f24 c12 nvcc_epdc hvio alt1 in keeper epdc_sdce0 d13 n24 b12 nvcc_epdc hvio alt1 in keeper epdc_sdce1 e13 p24 a12 nvcc_epdc hvio alt1 in keeper epdc_sdce2 d12 h21 c11 nvcc_epdc hvio alt1 in keeper epdc_sdce3 e12 j21 e8 nvcc_epdc hvio alt1 in keeper epdc_sdce4 d11 k21 d10 nvcc_epdc hvio alt1 in keeper epdc_sdce5 e11 d18 e6 nvcc_epdc hvio alt1 in keeper epdc_sdclk a13 k24 b13 nvcc_epdc hvio alt1 in keeper epdc_sdclkn b13 l24 d12 nvcc_epdc hvio alt1 in keeper epdc_sdle d18 m24 c15 nvcc_epdc hvio alt1 in keeper epdc_sdoe e18 v21 c13 nvcc_epdc hvio alt1 in keeper epdc_sdoed d19 r23 g16 nvcc_epdc hvio alt1 in keeper epdc_sdoez e19 u21 f16 nvcc_epdc hvio alt1 in keeper epdc_sdshr a10 h23 a8 nvcc_epdc hvio alt1 in keeper epdc_vcom0 g17 h24 b14 nvcc_epdc hvio alt1 in keeper epdc_vcom1 d20 w21 g15 nvcc_epdc hvio alt1 in keeper epito g4 d8 f5 nvcc_misc hvio alt1 in keeper extal ac5 ac5 w6 vdd2p5 analog ? ? ? gnd_kel aa7 aa7 t7 vdd2p5 analog ? ? ? i2c1_scl e1 a6 e1 nvcc_misc hvio alt1 in keeper i2c1_sda e2 b7 e2 nvcc_misc hvio alt1 in keeper i2c2_scl f1 a5 f1 nvcc_misc hvio alt1 in keeper i2c2_sda f2 b6 f2 nvcc_misc hvio alt1 in keeper i2c3_scl g1 a4 g1 nvcc_misc hvio alt1 in keeper i2c3_sda g2 b5 g2 nvcc_misc hvio alt1 in keeper jtag_mod v7 v5 t8 nvcc_jtag gpio alt0 in 100k pu jtag_tck w4 w4 r8 nvcc_jtag gpio alt0 in 100k pd table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
i.mx50 applications processors for consumer products, rev. 2 130 freescale semiconductor package information and contact assignments jtag_tdi aa4 aa4 u8 nvcc_jtag gpio alt0 in 47k pu jtag_tdo u7 v4 t9 nvcc_jtag gpio alt0 out-lo keeper jtag_tms y4 y4 r9 nvcc_jtag gpio alt0 in 47k pu jtag_trstb aa5 aa5 u7 nvcc_jtag gpio alt0 in 47k pu key_col0 b1 a9 b1 nvcc_keypad hvio alt1 in keeper key_col1 b2 a10 b2 nvcc_keypad hvio alt1 in keeper key_col2 c1 b9 c1 nvcc_keypad hvio alt1 in keeper key_col3 c2 b10 c2 nvcc_keypad hvio alt1 in keeper key_row0 d1 a8 d1 nvcc_keypad hvio alt1 in keeper key_row1 d2 b8 d2 nvcc_keypad hvio alt1 in keeper key_row2 d4 d7 c3 nvcc_keypad hvio alt1 in keeper key_row3 e4 a7 d3 nvcc_keypad hvio alt1 in keeper owire g7 d12 e5 nvcc_misc hvio alt1 in keeper pmic_on_req w1 w1 y3 nvcc_srtc gpio alt0 out-lo ? pmic_stby_req w2 w2 y2 nvcc_srtc gpio alt0 out-lo ? por_b ad2 ad2 y5 nvcc_reset lvio alt0 in 100k pu pwm1 f5 d11 e4 nvcc_misc hvio alt1 in keeper pwm2 f4 d10 e3 nvcc_misc hvio alt1 in keeper reset_in_b ac1 ac1 w3 nvcc_reset lvio alt0 in 100k pu sd1_clk p1 m1 r1 nvcc_sd1 hvio alt1 in keeper sd1_cmd r1 n1 p4 nvcc_sd1 hvio alt1 in keeper sd1_d0 r2 p2 r2 nvcc_sd1 hvio alt1 in keeper sd1_d1 p2 n2 p1 nvcc_sd1 hvio alt1 in keeper sd1_d2 r4 m2 p3 nvcc_sd1 hvio alt1 in keeper sd1_d3 r5 r4 p2 nvcc_sd1 hvio alt1 in keeper sd2_cd t4 j4 t1 nvcc_sd2 hvio alt1 in keeper sd2_clk u1 e1 t3 nvcc_sd2 hvio alt1 in keeper sd2_cmd v5 g1 v1 nvcc_sd2 hvio alt1 in keeper sd2_d0 t1 d1 r3 nvcc_sd2 hvio alt1 in keeper sd2_d1 t2 d2 u1 nvcc_sd2 hvio alt1 in keeper table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
package information and contact assignments i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 131 sd2_d2 v1 f1 w2 nvcc_sd2 hvio alt1 in keeper sd2_d3 v2 f2 t4 nvcc_sd2 hvio alt1 in keeper sd2_d4 v4 g2 v2 nvcc_sd2 hvio alt1 in keeper sd2_d5 u2 e2 u2 nvcc_sd2 hvio alt1 in keeper sd2_d6 u4 h4 r4 nvcc_sd2 hvio alt1 in keeper sd2_d7 u5 f4 w1 nvcc_sd2 hvio alt1 in keeper sd2_wp t5 g4 t2 nvcc_sd2 hvio alt1 in keeper sd3_clk ad16 t1 y14 nvcc_nandf hvio alt1 in keeper sd3_cmd ad17 t2 u16 nvcc_nandf hvio alt1 in keeper sd3_d0 ac15 v1 y17 nvcc_nandf hvio alt1 in keeper sd3_d1 ac16 v2 v16 nvcc_nandf hvio alt1 in keeper sd3_d2 ac17 r1 t16 nvcc_nandf hvio alt1 in keeper sd3_d3 aa17 u2 u15 nvcc_nandf hvio alt1 in keeper sd3_d4 aa18 p1 w17 nvcc_nandf hvio alt1 in keeper sd3_d5 y18 u1 u17 nvcc_nandf hvio alt1 in keeper sd3_d6 aa19 r2 v17 nvcc_nandf hvio alt1 in keeper sd3_d7 y19 u4 t15 nvcc_nandf hvio alt1 in keeper sd3_wp ad15 t4 w16 nvcc_nandf hvio alt1 in keeper ssi_rxc j7 ad12 h4 nvcc_ssi hvio alt1 in keeper ssi_rxd j5 ac14 f3 nvcc_ssi hvio alt1 in keeper ssi_rxfs h7 ad13 g5 nvcc_ssi hvio alt1 in keeper ssi_txc j4 ac13 g3 nvcc_ssi hvio alt1 in keeper ssi_txd h5 ad14 g4 nvcc_ssi hvio alt1 in keeper ssi_txfs h4 ac12 h3 nvcc_ssi hvio alt1 in keeper test_mode ac2 ac2 u4 nvcc_reset lvio alt0 in 100k pd uart1_cts h2 b4 j1 nvcc_uart hvio alt1 in keeper uart1_rts j2 b3 k2 nvcc_uart hvio alt1 in keeper uart1_rxd j1 a2 k1 nvcc_uart hvio alt1 in keeper uart1_txd h1 a3 h1 nvcc_uart hvio alt1 in keeper uart2_cts k2 b2 nvcc_uart hvio alt1 in keeper table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
i.mx50 applications processors for consumer products, rev. 2 132 freescale semiconductor package information and contact assignments uart2_rts l2 c2 nvcc_uart hvio alt1 in keeper uart2_rxd l1 c1 l2 nvcc_uart hvio alt1 in keeper uart2_txd k1 b1 l1 nvcc_uart hvio alt1 in keeper uart3_rxd l4 e4 k3 nvcc_uart hvio alt1 in keeper uart3_txd k4 d4 j2 nvcc_uart hvio alt1 in keeper uart4_rxd l5 d5 j3 nvcc_uart hvio alt1 in keeper uart4_txd k5 d6 h2 nvcc_uart hvio alt1 in keeper usb_h1_dn ac10 ac10 w10 usb_h1_vdda25, usb_h1_vdda33 analog50 ? ? ? usb_h1_dp ad10 ad10 y10 usb_h1_vdda25, usb_h1_vdda33 analog50 ? ? ? usb_h1_gpanai o y11 aa17 u10 usb_h1_vdda25, usb_h1_vdda33 analog25 ? ? ? usb_h1_rrefex t aa10 aa10 u9 usb_h1_vdda25, usb_h1_vdda33 analog25 ? ? ? usb_h1_vbus y10 aa16 v9 usb_h1_vdda25, usb_h1_vdda33 analog50 ? ? ? usb_otg_dn ac8 ac8 w8 usb_otg_vdda25, usb_otg_vdda33 analog50 ? ? ? usb_otg_dp ad8 ad8 y8 usb_otg_vdda25, usb_otg_vdda33 analog50 ? ? ? usb_otg_gpana io y7 aa14 v7 usb_otg_vdda25, usb_otg_vdda33 analog25 ? ? ? usb_otg_id y8 aa12 y7 usb_otg_vdda25, usb_otg_vdda33 analog25 ? ? ? usb_otg_rrefe xt aa8 aa8 w7 usb_otg_vdda25, usb_otg_vdda33 analog25 ? ? ? usb_otg_vbus y9 aa13 v8 usb_otg_vdda25, usb_otg_vdda33 analog50 ? ? ? vref m23 m23 k17 vddo25 analog ? ? ? wdog g5 d9 f4 nvcc_misc hvio alt1 in ? xtal ad5 ad5 y6 vdd2p5 analog ? ? ? table 84. alphabetical list of signal assignments (continued) pin name 416 mapbga ball number 416 popbga ball number 400 mapbga ball number pin power domain pad type iomux mux ctl after reset direction after reset iomux pad ctl after reset
revision history i.mx50 applications processors for consumer products, rev. 2 freescale semiconductor 133 6 revision history table 85 provides a revision history for this data sheet. table 85. i.mx50 data sheet document revision history rev. number date substantive change(s) rev. 2 05/2012 ? in table 1, "ordering information," on page 7 , added the following new part numbers: mcimx508czk8b, mcimx503cvk8b, mcimx503evm8b, mcimx502cvk8b, and mcimx502evm8b. ?in table 1, "ordering information," on page 7 , added a new column, t junction . ?in table 3, "package feature comparison," on page 8 , added a new row for 416 popbga package. ? updated figure 1, "i.mx50 system block diagram," on page 10 by removing ?ldox3? and ?dc-dc 1.2v.? ?in table 5, "special signal considerations," on page 17 , updated details for the following signals: dram_open/dram_openfb and dram_sdodt0/dram_sdodt1 ?in table 5, "special signal considerations," on page 17 , added new rows for the following signals: pop_emmc_rst, pop_lpddr2_zq0/zq1, pop_lpddr2_1.8v, and pop_nand_vcc. ? added section 4.1.2.1, ?13 x 13 mm mapbga package thermal resistance data.? ? added section 4.1.2.2, ?13 x 13 mm popbga package thermal resistance data.? ? added section 4.1.2.3, ?17 x 17 mm mapbga package thermal resistance data.? ?in table 11, "i.mx50 operating ranges," on page 24 , added footnotes for usb_otg_vdda25 and usb_otg_vdda33. ?in table 77, "vbus comparators thresholds," on page 100 , changed vbus input max current to 350 a. ? added section 5.2, ?13 x 13 mm, 0.5 mm pitch, 416 pin popbga package information.? ?in table 84, "alphabetical list of signal assignments," on page 123 : ?added a new column ?416 popbga ball number? ?changed ?usb_h1_vdda? to ?usb_h1_vdda25, usb_h1_vdda33? ?changed ?usb_otg_vdda? to ?usb_otg_vdda25, usb_otg_vdda33? ? replace mddr with lpddr1 throughout the document. rev. 1 10/2011 ? table 5, "special signal considerations," on page 17 changed chrg_det_b to chgr_det_b. ? table 5, "special signal considerations," on page 17 in the chgr_det_b signal remarks, added ?the maximum current leakage at this pin is 8.5 a.? ? table 5, "special signal considerations," on page 17 in the jtag_mod remarks, changed ?pull-down? to ?pull-up, by default? and added ?if jtag port is not needed, the internal pull-up can be disabled in order to reduce supply current to the pin.? ? table 14, "maximum supply current consumption," on page 27 in the 11 th row under the supply column, changed vddo2p5 to vddo25. ? table 77, "vbus comparators thresholds," on page 100 changed chrg_det_b to chgr_det_b. ? table 5, "special signal considerations," on page 17 for 416 mapbga, dram_sdclk_0 pin number was changed to n24 and dram_sdclk_0_b pin number was changed to m24. ? table 5, "special signal considerations," on page 17 for 416 mapbga, dram_sdclk_1 pin number was changed to t20 and dram_sdclk_1_b pin number was changed to r20. ? table 5, "special signal considerations," on page 17 for 416 mapbga, dram_sdqs0 pin number was changed to p23 and dram_sdqs0_b pin number was changed to p24. ? table 5, "special signal considerations," on page 17 changed pad type of pin dram_calibration to dramcalib. ? table 5, "special signal considerations," on page 17 changed pad type of pins dram_sdclk_0, dram_sdclk_0_b, dram_sdclk_1, dram_sdclk_1_b, dram_sdqs0, dram_sdqs0_b, dram_sdqs1, dram_sdqs1_b, dram_sdqs2, dram_sdqs2_b, dram_sdqs3, and dram_sdqs3_b to dramclk. rev. 0 07/2011 initial release.
i.mx50 applications processors for consumer products, rev. 2 134 freescale semiconductor revision history document number: imx50cec rev. 2 05/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm is the registered trademark of arm limited. arm cortex tm -a8 is a trademark of arm limited. ? 2012 freescale semiconductor, inc. all rights reserved.

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